Logic Design

Customer Support Solution 11014718

stump1019 — Thu, 19 Nov 2009 19:24:06 GMT

First of all let me say that this shouldn't be this difficult to find. I've never had to do this before and I've been looking for almost a half hour trying to find this article. Anyone have any idea where I might find Allegro Design Entry HDL Customer Solution 11014718? Thanks, Mike.

Does anyone have the 0.18um standard cell library?

learnlearn1 — Thu, 19 Nov 2009 19:14:08 GMT

Hi I want FSA0A_C 0.18 um ASIC standard cell library for synthesis. Could email me the library file if anyone has it?

Many thanks!

Constraint two path in the design to have equal propagation delay

diablo — Mon, 16 Nov 2009 19:07:42 GMT

Hi all,

How to contraint two path in the design to have equal propagation delay using SDC file in RTL compiler? For example, is there a way to specify in RTL compiler to make path point A to point B have equal propagation delay as path point A to point C in the design?

Thanks for your time.

Regards.

TAP Control signals

Leo1008 — Thu, 12 Nov 2009 12:03:08 GMT

Hi,

I read that the TAP state machine generates control signals like Clock_IR, Shift_IR, Update_IR, Clock_DR, Shift_DR and Update_DR.

Out of these I could figure, if I'm not wrong, that the shift and update control signals would be asserted upon reaching the corresponding state in the state machine.
However I'm not quite sure when the Clock_DR/IR control signal would be asserted. Would it be before entering the capture state or while in the capture state??

Thanks

Insiya

User defined data registers in JTAG

Leo1008 — Thu, 12 Nov 2009 11:43:47 GMT

Hi all,

I have just started reading about jtag boundary scan architecture and need to implement it
in an application where jtag port is used to read and write to register banks.
For this purpose, I need to add two user defined data registers ( one for reading and writing each).

I want to know how to customize the architecture in order to insert the above said user defined registers .

Also, I need to define two user defined instructions for the same purpose of sending and receiving data from register banks. From my understanding, I presume that can be done by defining these instructions in the BSDL file? Is my understanding correct?

Thanks.

Insiya

error occured while importing netlist

gopinathkannan — Thu, 12 Nov 2009 05:21:25 GMT

the following error occured which is,

ERROR(302) Device library error detected

for eg,

Pin 'HBPRI#' for function 'TYPE8' on device '945GMS' has swap/pinuse inconsistency.

Reg .VCD file generation

Music — Wed, 11 Nov 2009 17:14:59 GMT

Hi,

I need to run power analysis . so i need .vcd file. So can any ione say how to generate a .vcd file. I have model sim, Xilix, RC compiler , SoC Encpunter 8.1 . From these can i generate a .vcd file if so let me know the steps pla.. i have lib, lef , sdc, sdf.etc file swith me.. plz help me.. i need some steps....i asked in digital forum they requested me to post here... i.e in this forum...

Propagated clocks

gchalive — Sat, 31 Oct 2009 01:04:54 GMT

How do i set propagated clocks in RC. Is there an equivalent command to the synopsys command set_propagated_clocks. Thanks

Verilog Netlist to VHDL Netlist?

Scrivner — Tue, 20 Oct 2009 20:26:18 GMT

Does anyone know of a tool to convert a Verilog gate-level netlist to a VHDL gate-level netlist? And should SDF annotate to the VHDL without problems?

Thanks,

Bart

Upcoming Conformal Products 9.1 Release

petrak — Fri, 09 Oct 2009 23:44:18 GMT

The Conformal 9.1 release is scheduled for early November 2009. This release will feature advancements in datapath analysis, hierarchical compare, multi-threading use, retiming support, improvements in ECO patch quality, and physically/timing aware GA array and standard cell spare gate mapping for Post-mask ECO. Additionally, there are enhancements in the Conformal Low Power verification flow including interoperability support for power intent languages.

We hope you have participated in our LEC 9.1 Drop-in Beta program. We encourage customers to participate in this program to get early access, understanding, and testdrive some of our upcoming release features. Please contact us if you wish to participate in our Beta Program for future software releases.

Bassilios Petrakis

Marketing Director for Conformal Products

Synthesize problem

Hava — Fri, 09 Oct 2009 09:02:52 GMT

Hi there, I'm trying to synthesize my degin with CadenceRC. I have a makefile and a tcl scirpt to make the synthesization. At first it works, then I must did something wrong I cannot synthesize any more. It showed messages like this:

make: Circular my_design.vhd <- my_design.vhd dependency dropped

make: nothing to be donefor 'syn'

make: no rule to make the target . stop.

I cannot findout where is wrong.Could someone help me out of here?Thank you.

Tool: Cadence Encounter RC v08.10

Design: VHDL

Attachment: design source code, makefile, syn.tcl

Specifying timing path for synchronous circuits

gchalive — Thu, 01 Oct 2009 01:43:27 GMT

Hi..

How do I specify a timing path of a synchronous circuit in Cadence RTL Compielr. What I want is to synthesize the circuit considering the path I specified as the critical path.

Suppose I have two seqential elements and a combinational logic in between that generates the clock of the second flip flop, I want my critical path delay to be (clk_q)FF1+Comb_delay+(clk_q)FF2. Is there a command in RC that does this.

Thanks

STA in RC

gchalive — Thu, 01 Oct 2009 19:20:46 GMT

Hey,

Can RC perform the static timing analysis. How do I report set up and hold time violations in RC.

Thanks

CadenceRC area report

Hava — Wed, 30 Sep 2009 08:06:03 GMT

Hi, I've got a area report for my design.

Gate    Instances   Area      Library
------------------------------------------
FD1QLLP        15 423.612    CORE9GPLL
FD1SQLLP       1   34.292    CORE9GPLL
HA1LL            14 254.167    CORE9GPLL
IVLLX05           2    8.069    CORE9GPLL
------------------------------------------
total              32 720.140

Could anyone tell me what measurement is used to get the area number (associating with each type of gates)? And how can I transfer this area result into NAND count respectively? Thanks~

Synthesizing Mixed Verilog-VHDL in RTL Compiler?

Scrivner — Fri, 25 Sep 2009 22:03:36 GMT

Does anyone have experience using RTL Compiler with a design that includes mixed Verilog and VHDL code? I will have a design soon that is verilog at top level with some small verilog modules instantiated, but the bulk of the design will be an instantiation of a large VHDL hierarchy.

Is it as simple as creating an instantiation of the VHDL module in the top level verilog and then reading in all of the RTL into RC? Or are there some tricks that I'll need to know? Any special switches in RC that I should know about for mixed Verilog-VHDL synthesis?

Thanks in advance for any help anyone can provide!

Bart

In encounter RTL compiler, how can I apply speed or size optimization options

learnlearn1 — Wed, 16 Sep 2009 16:23:06 GMT

In Synopsys, HDL files can be synthesized with speed or size optimization options.

How can do the same thing in the rc RTL compiler when I synthesize a file?

Thanks!

How do I connect an instiantiated library clock gating cell to scan chains?

maxb — Tue, 25 Aug 2009 13:55:36 GMT

In our design, we instantiate a library clock gating cell ("DLSG1") to do functional clock gating at the RTL level. This cell has an SE input which is left unconnected in the RTL code since no other DFT signals are present at this stage:

module my_cg (input clk, input enable, output clk_gated);

DLSG1 u_cg (.C (clk), .E (enable), .SE (), .GCK (clk_gated));
endmodule

How can I connect the SE input of this cell to the shift_enable signal which is defined during synthesis?

I have defined scan chains and test control signals at the top level, but when I run check_dft_rules I get warnings that the clock is not controllable:

Warning : DFT Clock Rule Violation. [DFT-301]
: # 0 <vid_0_clock>: internal or gated clock signal in module 'my_cg', net 'clk_gated', inst/pin '.../my_cg/GCK' [CLOCK-05]
: Clock signal is not controllable. Affected registers will be excluded from scan design.

Unit names for vhdl and verilog

ras thomas — Tue, 18 Aug 2009 11:42:39 GMT

Hi!

I have some trouble with the case senstivity of unit names in desing libraries of IUS 8.2. Up to now the design has only source files in vhdl and everything went fine. But now i had to import verilog files from a netlist generator for verifying timing delays. This results in doubeling of unit names, due to the case sensitivity in verilog and the insensitivity in vhdl.

for example:

vhdl design:

entity newLogicCircuit is
port ( xyz: std_logic; );
end newLogicCircuit;

verilog imported file for timing simulation:

module newLogicDesign (xyz);
input xyz;
...
endmodule

Resulting trouble in compiled library:

newLogicDesign
module

newlogicdesign
entity
behaviour

What I would like to have is one unit in library with all views for this unit within one unit only not in two seperate ones, because they all belong together.

Currently the only way to do this is writing all unit names in lower case in vhdl, resulting in generated lower case names in verilog as well. But this makes this names rather hard to read, because its hard to seperate each word.

For ncvlog there exists a special command line option (- upcase) which can force every verilog name to be compiled as upper case name into working library. That doesn't helps with this issue because all vhdl units are converted to lower case, but maybe there exists a way to force every verilog name to lower case. However I havn't found such a option.

Does somebody know a solution or workaround for that issue?

Regards,

Thomas

why IUS so sloooooow ?

duckfly — Wed, 29 Jul 2009 01:06:46 GMT

I tried the same OVM based testbench on IUS8.2-S012 and VCS0906 , and there is an amazing performance contrast !

VCS is 7X more faster than IUS !

UPF to CPF conversion

vicky — Fri, 24 Jul 2009 11:35:11 GMT

Is there any utility which would do a conversion of an UPF file to CPF file. I have a testcase which has been implemented using UPF and now I am planning to implement the same using CPF. I did a manual conversion of the commands to create the power domains but I feel that the way the switch cells and isloation cells are defined in the CPF and UPF is very difficult to convert from it.

Power nets vs offpage connector

Jamez — Fri, 17 Jul 2009 22:35:10 GMT

How can I get a Power net called V5P and an offpage conn. Called V5P to be the same net? Capture seems to create 1 net called V5P and another called V5P_######## (random number).

Thanks,

Jim

ETS software crash

MarceloLucena — Wed, 13 May 2009 19:53:09 GMT

Hi,

The ETS software closes unexpectedly when I try to load a verilog gate-level netlist generated from RTL Compiler. In the console, I loaded the library file with the read_lib command and it worked ok, but when I use the read_verilog command to read the netlist, the program closes unexpectedly. I tried in a different machine but I got the same problem. The same happened when I tried to load the netlist using the GUI.

This verilog netlist has a file size of 3.7MB and over 77000 lines, I wonder if that could be a problem and if the ETS software has a design size limit requirement. I tried a much smaller design and it worked perfectly.

Thanks,

Marcelo

Problems Saving in .SCH format

xmoix — Thu, 14 May 2009 10:39:17 GMT

Hi!

Actually I'm experimenting some problems when I'm trying to save one Capture 16.2 schematic (.DSN) in .SCH format.

When Capture is starting to save, first it says that the destiny directory isn't empty, and then it adverts to read the session log.

Also I get an error like [Xnnnnnnn] and I can't see it because the aplication crashes suddenly during the process.

Will anyone help me?

Thanks a lot!

license error on my system

havisingh — Wed, 29 Apr 2009 14:19:58 GMT

I have been using orcad 15.7 on my laptop and recently I loaded an anti-virus program. After that I have license error and a window pops up where it tells me that there is license error in flexid at 1520@home where as my ID is 1800@home. I run the license file and the utility but same error persists. Please help.

No binary/Encrypted TCL(tcl compiler) support in all cadence tools, but Yes in Synopsys!

iceda — Thu, 30 Apr 2009 23:05:25 GMT

Currently everybody is talking out IP protection, including all TCL commands, but it seems that Cadence didn't do good job for this kind of IP proctection unlike synopsys. Now all byte-code TCL is supported very well in all synopsys tools, but not a tiny support in all cadence tools!