Functional Verification

Clocking blocks /cycle based sampling and driving

hipooja — Wed, 04 Nov 2009 09:44:46 GMT

Hi,

I read that clocking block / cycle based simulation in SV promotes reusability.Why is that so? I understand that interface definition simplifies the signal connection How does this promote reusability?

Regards,

Pooja Vaishnav.

SV: Coverage of assertions (only count hits??)

rossbthompson — Fri, 20 Nov 2009 20:37:13 GMT

I was under the impression that assertions would be included in functional coverage. It seems that I am only get the evaluated assertions, not ones that have not fired. Is it possible to include the un-evaluated assertions as coverage holes?

I have multiple instances of the same checker (sv module), but I see different totals under the assertion column. I am new to SV, so it could be something basic.

Below is an example of what I see, all of the lines are instances of the same checker. The issue is that the assertion total is different

Coverage of immediate sub-instances:
Total    Assertion    CoverGroup Weighted    CoverGroup Bins    Name
80%    100% (5/5)    60% (1)    47% (8/17)    dbxxt_dgl
73%    100% (6/6)    46% (1)    29% (5/17)    dbxxxd_det
73%    100% (6/6)    46% (1)    29% (5/17)    dbxxxt_det
73%    100% (5/5)    46% (1)    29% (5/17)    dixxrm_det
73%    100% (6/6)    46% (1)    29% (5/17)    dbxxc_det
73%    100% (4/4)    46% (1)    29% (5/17)    dxxxxxp_det
80%    100% (4/4)    60% (1)    47% (8/17)    dxxxxg_det
73%    100% (4/4)    46% (1)    29% (5/17)    dxxxxx_det
73%    100% (5/5)    46% (1)    29% (5/17)    dxxxxin_det
73%    100% (5/5)    46% (1)    29% (5/17)    dxxxxxwv_det
73%    100% (6/6)    46% (1)    29% (5/17)    dxxxxg_det
73%    100% (4/4)    46% (1)    29% (5/17)    dxxxv_det
73%    100% (4/4)    46% (1)    29% (5/17)    dxxxxx_det
73%    100% (4/4)    46% (1)    29% (5/17)    dxxxxt_det
73%    100% (6/6)    46% (1)    29% (5/17)    dixxxctive_det
63%    100% (2/2)    26% (1)    18% (3/17)    dxxxtive_det
78%    100% (6/6)    56% (1)    41% (7/17)    dxxxtive_det
78%    100% (6/6)    56% (1)    41% (7/17)    dxxxxxactive_det

Command:

report_html -output cov_web -all fd -inst xxx.xxxx.*

version 08.20-s015

unique and priority in SV

hipooja — Wed, 04 Nov 2009 08:36:51 GMT

I wanted to check if my understanding on the usage of unique and priority keywords is correct or not.Unique i understand is a keyword used to tell the synthesis tool to infer a simple mux.The statements would be evaluated in parallel and which ever becomes true ,is executed.The advantage of using 'unique' keyword is that it gives warning messages when the conditions are not mutually exclusive,and hence would be best suited for applications such as processing a read and write request to memory ,read and write requests must not overlap,incase they do ,it should be reported as an error.

Priority keyword is to inform the synthesis tool ,to infer a priority mux.This may be used to implement a priority arbitration mechanism.

Conditions are evaluated in priority.

Examples of the usage of these keywords used in TB which you have worked on will be appreciated.

Regards,

Pooja

Garbage collection problem

spark — Thu, 04 Jun 2009 07:24:38 GMT

Hi all,

I encounter a problem during the simulation. If the simulation time is very long then "Doing garbage collection" message always appear, the simulation will not continue smoothly. I dont know where is problem. Do I need set some specman configure to avoid this problem?

The environment is NC-SIM (IUS) 8.1 and Specman(SPMN) 8.1.

[DPI] Transfer struct between SV and C

YM KIM — Wed, 18 Nov 2009 08:17:23 GMT

Hello all,

I'd like you to give me any advice regarding DPI, especially "import", usage.

I'd like to transfer data from C to SV. For example, my C code internally has struct type and function that returns struct and my SV code imports that function to get that struct.

Is it possible case? If so, please let me have, too.

Thank you in advance.

problem with AXI uVc

eyal — Tue, 10 Nov 2009 08:55:52 GMT

Hi all

i facing some problem setting the storbe field fo vr_axi_transfer.

the setting of a new strobe doesn't change the address offset and the data that need to be writen ? why ?

and how it can be fixed ?

more over the does the strobe aligened with the endiannity ?

Eyal

New to SV: Disabling of assertions from a task?

rossbthompson — Tue, 17 Nov 2009 15:27:00 GMT

I am in the process of creating SV checkers for an existing environment. I am trying to find a way to disable all assertions for a given test. The test in question is a force/check style which throws off all of the assertions. I have seen a method of doing this from TCL, but would like to do it from a task (current test method).

Any recomendations appreciated

Thanks,

Ross

Usage of verilog compiler directive in TCL

usiciliani — Thu, 12 Nov 2009 17:19:55 GMT

I'm using TCL scripts to stimulate a verilog database (based on task - schedule statement).

Is there a way to use verilog compiler directive (like `define) in TCL?

night run script using irun

eyal — Thu, 12 Nov 2009 13:51:26 GMT

Hi all

i was trying to to write c-shell script that runs a while loop and each iteration runs irun with -batch -exit option.

the problem is that in each test end the script get stuck in ncsim.

is there any way to configure ies through irun to close itself and re-open in the next iteration ?

i will also be happy to another approach to preform this task(how you run night runs ?).

best regards Eyal

C DPI compilation error

abhingp01 — Fri, 13 Nov 2009 12:10:28 GMT

Hi all,

I am checking my OVC against existing eVC. My OVC has some DPI interfaces with C-code.

C-Code is as follows:

#include<math.h>
#include"svdpi.h"

int ilog2_inC(int val)
{
return (log2(val));
}

int ipow_inC(int val)
{
return(pow(2,val));
}

I am using it in my monitor class of OVC.

Following statements imports it:

import "DPI-C" pure function int ilog2_inC(int logchk);
import "DPI-C" pure function int ipow_inC(int logchk);

But on compiling I am getting following error:

ncsim: *F,NOLWSV: Unable to load the default library libdpi.
OSDLERROR: ./libdpi.so: cannot open shared object file: No such file or directory or file is not valid ELFCLASS32 library..

Kindly help for same.

Regards

Abhishek

Sparse memory support

abhingp01 — Mon, 16 Nov 2009 04:41:59 GMT

Hi all,

I need to implement quite a large amount of memory (4 GB ) in my OVC.

For which Sparse memory modelling will be most efficient one.

I am currently using Cadence IUS2.0 and need to know if cadence supports sparse memory modelling.

I will really appresiate if you could suggest some document on "sparse memory modelling" .

Thanks in advance.

Regards
Abhishek

eVC config_wizard

spark — Thu, 12 Nov 2009 13:58:59 GMT

In AXI eVC package there is a config_wizard directory, it seems that it can generate configuration file automaticaly. But I dont know which tool is needed to do this generation and how do it. Would some one tell me, thank you.

My first verification environment in SV

Leo1008 — Mon, 26 Oct 2009 11:21:23 GMT

Hi all,

I am a new user of SystemVerilog and have been asked to develop a simple verification envirionment, wherein the DUT can be blank.

I have to concentrate on the generator, driver and interface blocks to start with. I started with writing classes for the mentioned blocks but I am not able to integrate interface with classes. Can someone help me out with this? And may be you could also share a short example so that i know what my environment shall look like

Thanks

lnternal error / Elaboration error ius81

Eder — Sun, 12 Apr 2009 15:48:01 GMT

Hi,

When using ius, i'm getting this strange error

file: ./INCA_libs/irun.lnx86.08.10.nc/svpplib/tb.sv
                Caching library 'worklib' ....... Done
        Elaborating the design hierarchy:
        Top level design units:
                tb
        Building instance overlay tables: .................... Done
        Enabling instrumentation for coverage types: functional
        Generating native compiled code:
                worklib.tb:sv <0x7a91fa59>
ncvlog_cg: *F,INTERR: INTERNAL ERROR
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: ncvlog_cg       08.10-s008
HOSTNAME: linux-pzu3
OPERATING SYSTEM: Linux 2.6.27.21-0.1-default #1 SMP 2009-03-31 14:50:44 +0200 x86_64
MESSAGE: gq_cab_to_tab - not a CAB
-----------------------------------------------------------------
ncelab: *E,CUVCGF: Code generation for worklib.tb:sv <0x7a91fa59> failed.
ncelab: *F,CGFAIL: Code generation failed for one or more modules.
irun: *E,ELBERR: Error during elaboration (status 2), exiting.

I wonder if somebody could even get me some advices about that, or any hints do find the origins of this error.

executing ncsim commands from verilog using system task

Arturi — Fri, 06 Nov 2009 17:25:38 GMT

Hi all,

I would like to be able to execute ncsim tcl commands from my verilog code.So intead of sourcing a tcl file at the beggining of the simulation, I would like my design to react on events and source the tcl script on its own.

something like:

@(posedge event_signal)

$source_tcl_script("./my_ncsim_commands.tcl");

I was wondering if cadence has implemeted a system task for that. Or how could I implement such.

Cheers

updating Specview's SPECMAN_PATH after it has been launched...

avidane — Mon, 09 Nov 2009 13:41:58 GMT

Hi,

Here's an annoying situation I often find myself in...I do something like:

specview -p "load x_top.e"

only to find out after a minute or two that specman couldn't find one of the files because I didn't set SPECMAN_PATH properly.

Trying to fix this by typing:

> shell source setenv SPECMAN_PATH ${SPECMAN_PATH}:bla

does not help, and neither does any other option I've tried so far...

anyone knows if this could be done somehow?

Thanks,

Avidan Efody,

Verifigen

www.specman-verification.com

event questions from newbie

enchanterchi — Mon, 09 Nov 2009 02:03:50 GMT

Dear Sir/Madam: I am a newbie of verification and specman. I have a question about EVENT in specman e: Can I create a event with is consisted of some other event, such as event CONSISTED_e = (@start_e or @stop_e or @clock_rise)? If it is possible, how could identify which is the cause of the CONSISTED_e in code? For example: my_method () @CONSISTED_e is { if (CONSISED_e is caused by @start_e) { // do something }; if (CONSISTED_e is caused by @(stop_e) { // DO SOMETHING }; and so on. Thanks.

Components of System verilog VE

Leo1008 — Wed, 04 Nov 2009 10:55:26 GMT

Hi,

I am new to writing verifcation environments and so wanted some briefing about the same. I have written one simple VE uptill now wherein I used as components an object, a generator, a driver, DUT, an output monitor, a scoreboard and an interface. I wrote a program block for the testbench with instances of the object, driver( which was extended from the generator), interface, monitor and the scoreboard. But I understand that the testbench should ideally include instances of only the DUT, VIP/VE and the monitor/checker.

I am not sure what the VIP/VE block should contain. Also how to pass commands to all these components from the Test?

It would be really nice if you could provide me with a sample env for reference.

Ref to variables

Leo1008 — Thu, 05 Nov 2009 08:20:46 GMT

Hi,

I wanted to know if I can pass, to a class method , references of variables not defined in that class??

Insiya

Error- uninitialized virtual interface object

akshay jog — Sun, 08 Nov 2009 04:08:09 GMT

hi, I have following error when simulating some ovm code "uninitialized virtual interface object" Can some one explain to me , what does this error mean and how to fix it?? after this error message it shows me the line in my code so pasting that part of code as well //***************************** virtual task reset_signals(); @(negedge vmif.i_aresetn); // error at this line----------------------- //write address signals vmif.i_awid_m

Active/Reactive regions

Leo1008 — Wed, 04 Nov 2009 11:04:48 GMT

Hi,

I have often come across the terms active and reactive regions of simulation in many of the SV tutorials, but haven't figured what they actually mean yet. Can you please elaborate on these.

Thanks

Difference : Semaphores and Mailboxes

hipooja — Wed, 04 Nov 2009 09:27:31 GMT

Hi,

The diffference i understand between usage of semaphore and mailbox is as follows

--Semaphores canot be used for data transfer between two concurrent processes ,however it helps in synchronizing them.As an example if two parallel processes lets say two different drivers are driving a same set of signals ,then to avoid contention it becomes necessary to use semaphores.

Mailboxes can be used to transfer data between two concurrent processes ,lets say our DUT supports 2 different bus protocols for accessing register space.We would have a scenario wherein we write a register from one bus driver and read it from the other bus

monitor,in that case we need to pass address and the expected data from the register or atleast the address incase we have a shadow register implemented in the Testbench

Is this a correct understanding.Please provide with examples as i am sure such features are frequently used in VE dev

Are channels fundamentally mailboxes?

Regards,

Pooja Vaishnav

Using struct and Union

hipooja — Wed, 04 Nov 2009 08:57:20 GMT

Hi,

I have used class to model different parts of VE ranging from the data structure to drivers ,generator , monitor ...Class is a collection

of different data types so is a struct and a union.The difference i know is that union occupies memory equal to its largest data element unlike a struct or a class and secondly a struct can contain a union ,even a class can have a nested class object.

My questions is ,where do we use struct and union.Have you used them in modelling data or any other element of the VE and why?

How do i differentiate as to where should i be using a class/struct/union.

Regards,

Pooja Vaishnav

changing the color of displayed messages

Arturi — Tue, 03 Nov 2009 00:09:35 GMT

Hi all,

is there a way to change the color of messages being displayed in ncsim's console?

My verification environment has lots of $display statements. Some are debugging messages some are error messages.

I would like to change the color of the error messages.

any hint?

Cheers

Event ordering in SV and Verilog

hipooja — Wed, 04 Nov 2009 09:09:59 GMT

Hi,

I read that the event ordering is better in SV.In what ways is it better.I see that the program block execution in which we usually write the testcase occurs in the reactive region ,after the blocking and non-blocking assignments have been evaluated and assigned ,which is a good feature ,How is that so? Would races in asignmentaffect the testcase?

Regards,

Pooja Vaishnav