Digital Implementationhttp://www.cadence.com/Community/forums/29.aspx<b>Moderators:</b> Lli-Siang, Chrystian Cloutier-Roy, Bob Dwyer, Kari Summers.enCommunityServer 2007.1 (Build: 20917.1142)Re: EMIG violations at VDD/VSS padshttp://www.cadence.com/Community/forums/thread/19883.aspxThu, 06 Aug 2009 16:29:23 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:19883Kari0http://www.cadence.com/Community/forums/thread/19883.aspxhttp://www.cadence.com/Community/forums/commentrss.aspx?SectionID=29&PostID=19883<p>&nbsp;What do the vias look like at that location? You may need a bigger via array.</p>EMIG violations at VDD/VSS padshttp://www.cadence.com/Community/forums/thread/18889.aspxWed, 01 Jul 2009 12:35:19 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:18889spach0http://www.cadence.com/Community/forums/thread/18889.aspxhttp://www.cadence.com/Community/forums/commentrss.aspx?SectionID=29&PostID=18889<p>hi,</p><p>&nbsp; i am having&nbsp;EMIG violations concentrated on I/O wires connecting VDD pad&nbsp;to core ring. please can any one suggest different solutions to fix them.&nbsp;</p><p>please tell me the basic steps should be followed to fix EMIG violations</p><p>&nbsp;</p><p>regards</p><p>spach</p>