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<?xml-stylesheet type="text/xsl" href="http://www.cadence.com/Community/utility/FeedStylesheets/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>PCB Design</title><link>http://www.cadence.com/Community/forums/27.aspx</link><description>From schematic to autorouting what are your challenges in producing high-speed designs?</description><dc:language>en</dc:language><generator>CommunityServer 2007.1 (Build: 20917.1142)</generator><item><title>Auto-Router Clearence Conflicts</title><link>http://www.cadence.com/Community/forums/thread/18945.aspx</link><pubDate>Thu, 02 Jul 2009 17:32:08 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:18945</guid><dc:creator>PherricOxide</dc:creator><slash:comments>0</slash:comments><comments>http://www.cadence.com/Community/forums/thread/18945.aspx</comments><wfw:commentRss>http://www.cadence.com/Community/forums/commentrss.aspx?SectionID=27&amp;PostID=18945</wfw:commentRss><description>&lt;p&gt;I have a placed and routed reuse module that I&amp;#39;m attempting to connect to other modules, and use the auto-router to route between them. However, even when I choose to automatically route within Allegro PCB editor, even with the &amp;quot;preserve existing routes&amp;quot; option checked and the &amp;quot;delete conflicts&amp;quot; box unchecked, it will remove wires from inside the module due to clearance conflicts (at least I assume this is why, it has several hundred of them).&amp;nbsp; &lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;Where do I set the clearence conflict rules for the automatic router within Allegro PCB editor? When I do a DRC update, I find no errors on the wires that are getting removed (busses), so I have no idea what to toggle in the constraint manage. I set line to line spacing down to nothing and are still getting problems. &lt;/p&gt;</description></item></channel></rss>