System Design and Verification

Text properties in PVS ?

Selef — Tue, 17 Nov 2009 10:02:56 GMT

Hi to ALL,

does everybody know if and how we can use text properties on a DEVICE definition in a PVS (LVS) rule file.

For example in Assura this is made by extractDevice(......textProperty(..))

and in Calibre (SVRF format) by DEVICE....TEXT PROPERTY LAYER

During PVS LVS run there is a translation of SVRF format rules to PVS (masco format), but the run fails because of the TEXT PROPERTY LAYER command exist on SVRF format with user defined device error.

It seems that computational Build-In language of Calibre SVRF format (using text properties) is not translated properly to PVS (masco) format.

Is it something equivalent to the above statements in PVS (masco format) ?

Thanks,

Stavros

how to use PRBS in cadence

abhiii — Fri, 13 Nov 2009 06:02:06 GMT

Hi,

I would like to know if there is a prbs source which i can use to test some basic digital circuits like basic logic gates and flipflops and registers.

Command lines for PSPICE

Antonio 4 — Mon, 12 Oct 2009 12:58:35 GMT

Hola, I am a Spanish student and need information about PSPICE's commands lines to execute it from MSDOS

with C:\Program Files\OrCAD_Demo\PSpice\pspice.exe > C:\circuit_name.cir I can run PSPICE and that opens the file.cir but I don`t know how I can run the simulation of automatic form to generate the file "circuit_name.out"

Thanks and regards

PSpice Student Version?

markmick02 — Sun, 05 Jul 2009 20:24:36 GMT

I'm a student and find that PSpice 9.2 does not run well on XP/Server2003/Vista. Simulations do not keep their settings between runs, due to a "MarkerServer" error. I realize that PSpice 9.2 is no longer supported, but product is nearly useless on current OS's.

The Demo version works on XP/Vista, but is limited and will run few of my previous 9.2 schematics. I believe some of the IC models exceed the Demo limitations.

PSpice is a critical application for students. The real Cadence 16.2 is way too expensive for a student & the Demo version is too crippled. There's always NI's MultiSim, but my university uses PSpice. What is the solution to this dilemma? Install Win98 on some old PC?

Thanks...Mark

integration verification

hardware — Mon, 26 Oct 2009 15:26:13 GMT

Hi,

I am new to the verification environment. I am having a little trouble understanding the integration verifiation environment. Can some one please explain with example how looking at the hardware module can I see which signals to verify?

Thankyou.

Error: "...other program is busy..."

trieste — Fri, 17 Jul 2009 15:07:35 GMT

Running OrCAD 9.1. After creating a schematic and Simulation profile, when I hit the Simulate button, I get the following error window, labeled "Server Busy": "This action cannot be completed because the other program is busy. Choose 'Switch To' to activate the busy program and correct the problem." It provides two buttons that can be pushed: "Switch To" and "Retry".

"Retry" simply repeats the above and gives the same result.

"Switch To" gives the windows START menu, i.e. the list of programs. I can run any other of my programs, but when I go back to OrCAD, I get the same error window. If I run Task Manager, it shows only the OrCAD Capture task running (assuming I closed the program I just ran); no other tasks are listed. If I terminate it (this seems to be the only way of stopping it), when I run it again, or even if I create a new schematic and simulate it, it gives me the same result as above.

Any idea what is going on?

view layers

AKSHAYA — Mon, 19 Oct 2009 05:14:14 GMT

how we can select a single layer(top or bottom) to view in one shot without choosing subclasses on a layer like silkscreen, mask, pin, aeembly etc. hope somody can guide.

ncsim: *F,INTERR: INTERNAL ERROR

Sankara — Mon, 22 Dec 2008 09:17:34 GMT

Hi,

Test : DRAM write and read up to 2GB .

Simulation fails with the following error. Can anbody please help me out?

ncsim(64): 06.20-p001: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
ncsim: *F,INTERR: INTERNAL ERROR
Observed simulation time : 0 FS + 0
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: ncsim(64) 06.20-p001
HOSTNAME: XIDCTEA1
OPERATING SYSTEM: Linux 2.6.9-55.ELsmp #1 SMP Fri Apr 20 16:36:54 EDT 2007 x86_64
MESSAGE: System virtual memory limit exceeded (0x100000d8/0x2b6bba4010)
-----------------------------------------------------------------

Note : I had checked the enough physical memory and also virutaul memory available for the host.

Thanks,

Sankara

Problem with follow simple code

navis — Fri, 02 Oct 2009 15:24:26 GMT

Hello all,

I'm trying to use some simple class wirh SystemVerilog.

But NCSim dosn't work properly. What is the reason?

Here is the code which is very basic and veri simple:

module class_opt(output logic x);

class gen;
    task display_d(bit [3:0] in);
        $display ("You entered %d", in);
    endtask
    task sig_gen;
        #100;
        x = 1'b1;
        #100;
        x = 1'b0;
    endtask
endclass:gen

gen a = new();

initial begin

    in = 1;
    a.display_d(in);
    in = 2;
    a.display_d(in);
    in = 3;
    a.display_d(in);
    a.sig_gen;
    a.sig_gen;
    a.sig_gen;
    a.sig_gen;

end
endmodule

Any sugestions are welcome.

Thanks and regards

Which software to use?

theASICdude — Sun, 20 Sep 2009 20:17:48 GMT

hi all, A little confused here about all the available software out there. I need a software where I can design my circuit using verilog (RTL, behavioral) and then compile it (perhaps creating a netlist). Then be able to design a test bench and test out my circuit. My end product would be to get a GDSII file of my design. Would SoC encounter do all this? Thank you.

E-Planner export function error

natg9 — Wed, 16 Sep 2009 13:52:11 GMT

Hi ,

I am facing this absurd problem while trying to print to file option from a exported eplan in HTML format using the eplanner tool export feature.

The issue is that the text is not within the page margin of a A4 size even when shirnk to fit option is clicked

I have already used the shrink to fit option so kindly suggest some other work around to this problem.

Thanks

natg

Verilog, System Verilog and SystemC

jasonkee111 — Thu, 27 Aug 2009 07:23:35 GMT

i confused about these languages.

Can somebody clarify on it:
1. For RTL design, Verilog or System Verilog should be used?Most of the article about System Verilog focus on verification. Which language is easier to user and perform well?is there anything that verilog can do and system verilog cant? since a lot of hardware design engineer still use verilog for RTL design.

2. If the RTL design is written in Verilog, is it possible to use System Verilog to verify it?

3. Is it possible to mix Verilog, System Verilog and System C in one design? e.g Model in System C, the design written in verilog, System Verilog for verification

4. Since System C and System Verilog both also system level design, when to use System C and System Verilog?According to my understanding, System C is used in starting of system design in order to predict the performance of software and hardware while System Verilog is used in verification for RTL.

5. How to determine which portion in a system should go to softcore or hardcore?

6. I read a lot of threads that mention to use system verilog instead of system c for system level design(hardware design), is it correct? if in the case of SoC, where it involve the software and hardware, is system verilog have this kind of ability to synthesis(not sure the term to use) it?

Thanks and sorry if asking silly question(s)..

gnu subdir is missing in IUS82/tools/SystemC/lib and .../lib/64bit

NJSH — Fri, 31 Jul 2009 15:38:45 GMT

We do not have a GNU subdirectory in our IUS82/tools/SystemC/lib and lib/64bit/.
However, their is symbolic links pointing to that dirs and theses libraries are needed in our project.

What is wrong is our installation ?
Can someone just send us an archive file of theses gnu subdirs to fix the problem ?

Nicolas

CTS/IUS SystemC missing files ...

NJSH — Tue, 28 Jul 2009 19:42:36 GMT

I am trying to compile files from the CTS tutorial simply running the make command, but some files seems missing in the IUS installation. I have just done some minor modification in the Makefile to set the correct path for my tools and avoid deleting things without an explicit 'make clean' command.

ld: cannot find -lsystemc_sh

after searching for libsystemc_sh.so I found the file in /opt/IUS82/tools.lnx86/systemc/lib/64bit/ and /opt/IUS82/tools.lnx86/systemc/lib but they are symbolic links to gnu/libsystemc_sh.so and there is no gnu directory under theses path.

I had the same problem for TLM libraries (I have no $(NCROOT)/tools/systemc/tlm directory) but I have solved this using an external installation of TLM libraries and changing the search path in the Makefile.

There is lots of missing files (links pointing to a 'gnu' subdir) in systemc/lib

jpeg_idct_tutorial/xilinx> ls -l /opt/IUS82/tools/systemc/lib/64bit/
total 0
lrwxrwxrwx 1 softwares FRONT-END 27 2009-04-15 13:12 libncscCoroutines_sh.so -> gnu/libncscCoroutines_sh.so
lrwxrwxrwx 1 softwares FRONT-END 22 2009-04-15 13:12 libncscCoSim_sh.so -> gnu/libncscCoSim_sh.so
lrwxrwxrwx 1 softwares FRONT-END 21 2009-04-15 13:12 libncsctlm2_sh.so -> gnu/libncsctlm2_sh.so
lrwxrwxrwx 1 softwares FRONT-END 20 2009-04-15 13:12 libncsctlm_sh.so -> gnu/libncsctlm_sh.so
lrwxrwxrwx 1 softwares FRONT-END 12 2009-04-15 13:12 libovm.a -> gnu/libovm.a
lrwxrwxrwx 1 softwares FRONT-END 13 2009-04-15 13:12 libovm.so -> gnu/libovm.so
lrwxrwxrwx 1 softwares FRONT-END 19 2009-04-15 13:12 libsystemc_ar.a -> gnu/libsystemc_ar.a
lrwxrwxrwx 1 softwares FRONT-END 20 2009-04-15 13:12 libsystemc_sh.so -> gnu/libsystemc_sh.so
lrwxrwxrwx 1 softwares FRONT-END 12 2009-04-15 13:12 ncscpi.o -> gnu/ncscpi.o
lrwxrwxrwx 1 softwares FRONT-END 11 2009-04-15 13:12 qtmdc.o -> gnu/qtmdc.o
lrwxrwxrwx 1 softwares FRONT-END 11 2009-04-15 13:12 qtmds.o -> gnu/qtmds.o
lrwxrwxrwx 1 softwares FRONT-END 8 2009-04-15 13:12 qt.o -> gnu/qt.o
lrwxrwxrwx 1 softwares FRONT-END 15 2009-04-15 13:12 sc_fpi_nc.o -> gnu/sc_fpi_nc.o
lrwxrwxrwx 1 softwares FRONT-END 13 2009-04-15 13:12 sc_main.o -> gnu/sc_main.o

How can I fix this ?

Nicolas

---
Nicolas J. S. Hervé, PhD
SoPC architect
LSITEC, www.lsitec.org.br/dh

---

jpeg_idct_tutorial/xilinx> make
Test run at [...]
Test run in [...]/jpeg_idct_tutorial/xilinx
rm -rf run/*
ncsc_run -dynamic -gnu -I/home/CadenceServer/CTS09/tools/ctos/include -I. -VLOGEXT vg -SCTOP sc_main -I../tb/jpeg-6b -I../tb/xbus -I../Baseline/src -Imodel ../Baseline/src/xbus_hw_idct.cc -I/home/users/nicolas/Applications/SystemC/TLM-2008-06-09/include/tlm -DFUNC_COVERAGE -DTRANS_RECORDING ../tb/xbus/xbus_master.cc ../tb/xbus/xbus_mem_slave.cc ../tb/demo_top.cc ../tb/xbus_sw_jpeg.cc ../tb/xbus_master_transactor.cc ../tb/djpeg.c ../tb/jidctint.cc ../tb/jidctint_orig.c ../tb/tutorial_lib.v ../tb/jpeg-6b/cdjpeg.c ../tb/jpeg-6b/jcapimin.c ../tb/jpeg-6b/jcapistd.c ../tb/jpeg-6b/jccoefct.c ../tb/jpeg-6b/jccolor.c ../tb/jpeg-6b/jcdctmgr.c ../tb/jpeg-6b/jchuff.c ../tb/jpeg-6b/jcinit.c ../tb/jpeg-6b/jcmainct.c ../tb/jpeg-6b/jcmarker.c ../tb/jpeg-6b/jcmaster.c ../tb/jpeg-6b/jcomapi.c ../tb/jpeg-6b/jcparam.c ../tb/jpeg-6b/jcphuff.c ../tb/jpeg-6b/jcprepct.c ../tb/jpeg-6b/jcsample.c ../tb/jpeg-6b/jctrans.c ../tb/jpeg-6b/jdapimin.c ../tb/jpeg-6b/jdapistd.c ../tb/jpeg-6b/jdatadst.c ../tb/jpeg-6b/jdatasrc.c ../tb/jpeg-6b/jdcoefct.c ../tb/jpeg-6b/jdcolor.c ../tb/jpeg-6b/jddctmgr.c ../tb/jpeg-6b/jdhuff.c ../tb/jpeg-6b/jdinput.c ../tb/jpeg-6b/jdmainct.c ../tb/jpeg-6b/jdmarker.c ../tb/jpeg-6b/jdmaster.c ../tb/jpeg-6b/jdmerge.c ../tb/jpeg-6b/jdphuff.c ../tb/jpeg-6b/jdpostct.c ../tb/jpeg-6b/jdsample.c ../tb/jpeg-6b/jdtrans.c ../tb/jpeg-6b/jerror.c ../tb/jpeg-6b/jfdctflt.c ../tb/jpeg-6b/jfdctfst.c ../tb/jpeg-6b/jfdctint.c ../tb/jpeg-6b/jidctflt.c ../tb/jpeg-6b/jidctfst.c ../tb/jpeg-6b/jidctred.c ../tb/jpeg-6b/jmemmgr.c ../tb/jpeg-6b/jmemnobs.c ../tb/jpeg-6b/jquant1.c ../tb/jpeg-6b/jquant2.c ../tb/jpeg-6b/jutils.c ../tb/jpeg-6b/rdbmp.c ../tb/jpeg-6b/rdcolmap.c ../tb/jpeg-6b/rdgif.c ../tb/jpeg-6b/rdppm.c ../tb/jpeg-6b/rdrle.c ../tb/jpeg-6b/rdswitch.c ../tb/jpeg-6b/rdtarga.c ../tb/jpeg-6b/transupp.c ../tb/jpeg-6b/wrbmp.c ../tb/jpeg-6b/wrgif.c ../tb/jpeg-6b/wrppm.c ../tb/jpeg-6b/wrrle.c ../tb/jpeg-6b/wrtarga.c \
                -DCTOS_sim -DCTOS_MODEL=sim \
                model/jpeg_idct_tutorial_sim.v \
                -out ncsc_work_sim > log/ncsc_sim_v.log 2>&1
make: *** [ncsc_sim_v] Error 1

Here what I have at end of my ..../jpeg_idct_tutorial/xilinx/log/ncsc_sim_v.log:

jpeg_idct_tutorial/xilinx> tail log/ncsc_sim_v.log
building library ncsc_model.so
ld: cannot find -lsystemc_sh
collect2: ld returned 1 exit status
make: *** [libncsc_model.so] Error 1
ncsc_run: *E,TBBLDF: Failed to build test library
./libncsc_model.so

Instance handeling during simulation

WorkMan — Mon, 11 May 2009 12:48:11 GMT

Hi,

I am in the gate level power simulation phase. I have multiple (X100) instances of the same module and I do not want to run all of them as gate level modules just the ones I'm interested in capturing there signals. The only way I know how to do it is during compile time using `define. The problem is that we want to hold a single compiled design and not to have to compile each test again according to the test designer needs.

I would like to know if there is a way to define the instance module type during the simulator initial stages. Maybe SystemVerilog (Which I have no deep knowledge about) have an option to do so. I have tried using the $test$plusargs to differ between the different instances but it does not compile.

Thank you,

Issue while using already compiled libraries in IUS-8.2

Shunty — Thu, 07 May 2009 08:53:58 GMT

Hi All,

I am stucked at one situation while using IUS-8.2. I have some compiled libraries of vhdl in one INCA_libs folder.

Now In my System Verilog environment, I want to use those already compiled libraries of VHDL.

So I want to use the INCA_libs folder. what i did is,

While running my environment using irun, i used -cdslib switch to use those libraries.

irun -cdslib <PATH_TO_DESIGN_LIB_CDS_LIB> -f <VE.f>

Where, PATH_TO_DESIGN_LIB_CDS_LIB is a cds.lib file of the already compiled INCA_libs of design.

VE.f contains my Verification Environment related file.

Is this a correct way to do this? If not then please suggest correct one.

There is one strange problem occurs while using this command,

When the packages are imported inside the VE files shows this error,

import imp_1::*;
           |
ncvlog: *E,MULTPK (test.sv,7|11): Multiple (2) packages named "imp_1" were found in the searched libraries:
                -> found verilog_package worklib.imp_1:sv (VST)
                -> found verilog_package worklib.imp_1:sv (VST).
import imp_1::*;

To debug this,
When I opened cds.lib of my design's INCA_libs, last 2 statements were something like this,

DEFINE worklib worklib
DEFINE Mux worklib

When I removed the last statement which was for mapping purpose, The above error of importing the package got resolved.

But I did not get the successful loading of libraries because simulator gave me an error when I created an instace of Mux entity.

Anyone has any idea about this?

-Shunty

Cadence Systems Administrator support

jdgriggs — Thu, 25 Jun 2009 14:46:52 GMT

Hey Guys

I just have a couple of questions and if anyone knows or can help us out it would be appreciate. I'm a graduate student and our university is a member of the University Program with Cadence. However though we have access to the software and licenses, it is the University's responsibility for systems support i.e installs and PDK updates

Question 1: Where can a person go to learn how to do a proper install of Cadence from begining to end. Does Cadence offer a training course for this?

Question 2: We tried to hire some consultants however they weren't proficient enough to meet our needs, so our system is not working properly so if anyone knows an EDA Consultant close to the Greensboro, NC area or anyone that can come and take a look at our system and get us back working again would help us out alot.

Thanks

Pspice Simulation Error: Invalid Number in device C_C1, Divide

yujun61hugh — Fri, 10 Jul 2009 03:19:33 GMT

HI everyone,

I am trying to simulate a Class D output stage (including IRS2011, IRF7313 and LC filter), but the error comes out. "Invalid Number in device C_C1, Divide". Anyone knows its meaning and how to solve it? thanks

need to browse the device categories using itkDB.

Mikhail111 — Mon, 25 May 2009 09:28:13 GMT

Hello,
I need to browse the device categories in our automation tool using itkDB. Please suggest any appropriate way to do it. I know how to do it using SKILL but the task is to write the same in C++. Unfortunately I could not find in itkDB header any function like SKILL ddCat...(). What function set should I use? Where can I get an example of category browser (need to extract whole category tree)?
Thanks in advance.
Mike

Cadence session crash.

maskdesigner — Thu, 28 May 2009 17:10:09 GMT

Looking for some help on what the cause is when a Cadence session crashes when using Virtuoso : LE/XL Version 5.10.41_USR6.127.29.

There are 2 types of crashes.

First is while editing in the layout the whole session is killed and closed out. Here you will only see in a terminal window that a "segmentation fault" has occurred but a panic file does get created.

Second is while editing the session freezes and no panic file gets created.

We have hourly backups on the servers but with these episodes becoming more frequent we need to get to the cause of the crashes.

The servers at this point are not the problem and looking to see if the Cadence tool is triggered by something to cause the crash.

Thankyou in advance for any help here.

Some Commands are not logged

G Balaji — Mon, 11 May 2009 10:53:18 GMT

I’m currently engaged in a task where I should analyze multiple traces and mark label at some specific location of every trace. When I tried to use log commands and run commands, some of the commands like locating cursor on the next trace, selecting specific Y axis and mark label are not logged. Why?

ncshell : sytemc to verilog

Alok Sharma — Tue, 19 May 2009 16:50:26 GMT

Do I need to compile the systemc code with some particular flags in order to be able to translate ? Somehow I am not able to make ncshell "read" the module.

Thanks,

Alok

PSF, current probe, and Gmin

CadenceUserMT — Mon, 20 Apr 2009 11:03:51 GMT

I am new to Cadence and on this occasion I would like to ask three questions:

1. When I ran a spectre simulation, sometimes I got an error message requiring me to delete the psf file. This is quite annoying since I have to close Cadence, delete the psf file, and open Cadence again. I would like to know how to prevent this to occur again in the future.

- Warning -

<COM.cadence.awd.graph.GraphManager@1b7b407>

Plot command failed: cannot open data set tran-tran in results directory /home/simulation/test/spectre/schematic/psf

2. I tried to measure the DC base (B), collector (C), emitter (E) currents but when I selected the corresponding B/C/E transistor terminals, I got an error message: 'ERROR /T6/B is not a kept output.' I have set 'Select device currents (currents)' under Output-->Save all to ALL.

3. After I ran a transient simulation, I got this warning

Notice from spectre during IC analysis, during transient analysis 'tran'. Gmin = 1 pS is large enough to noticeably affect the DC solution. dV(T6.npn:int_b) = 15.4256 kV. Use 'gmin_check' option to eliminate or expand this report.

Where can I find gmin_check andmore importantly I don't know how to solve this problem? I also notice that the value of dv(...) is too large. What causes this?

Thanks

got an error while compiling VMM

x man — Wed, 27 May 2009 08:57:06 GMT

Hi,

I have downloaded the VMM IUS kit from "ovmworld.org ". Currently we are using IUS8.1 .But using this compiling i am getting this error. The irun.log file is as follows:

irun: 08.10-p002: (c) Copyright 1995-2008 Cadence Design Systems, Inc.
TOOL:    irun    08.10-p002: Started on May 26, 2009 at 14:40:57 IST
irun
    +incdir+/home/asif/systemVerilog/vmm-1.1/sv
    -sv
    log.sv
file: log.sv
ncvlog: *F,INTERR: INTERNAL ERROR
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL:    ncvlog    08.10-p002
HOSTNAME: pc8.kasurain.com
OPERATING SYSTEM: Linux 2.6.9-78.0.8.ELsmp #1 SMP Wed Nov 5 07:10:44 EST 2008 i686
MESSAGE: Unexpected signal #11, program terminated (null)
-----------------------------------------------------------------
irun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 250).
TOOL:    irun    08.10-p002: Exiting on May 26, 2009 at 14:40:57 IST (total: 00:00:00)

is it possible to get the older version of VMM so that we can run it from IUS8.1 ?

Asif

Systemverilog issues are not covered by Cadence.

Eduardo Briao — Tue, 02 Jun 2009 12:36:44 GMT

Hi,
I would like to understand some points about Systemverilog cadence simulator implementation.
I noticed that SystemVerilog of Cadence (irun 64 - v 08.20-p001: ) does not implement or has different code styles from standard Systemverilog (example: Accellera's manual of Systemverilog has different points from systemverilog used in irun cadence. ).
I want to understand the Systemverilog, and I am following a lab from www.testbenches.in (verification of a switch).
However, when I compile and elaborate the Systemverilog using "irun", a lot of errors have been generated.

I could fixed the great number of errors and even mistakes. However, some issues keep opened such as undesirable behavior/mistakes or issues were not implemented in the irun.
I got the original code from www.testbenches.in. However, there is a case that I cannot fixed (case 4).

Let`s analyse these examples:

*******************************
*******************************
Example 1:
Original code from site www.testbenches.in.
////////////////////////////////////////////////
interface mem_interface(input bit clock);
logic [7:0] mem_data;
logic [1:0] mem_add;
logic       mem_en;
logic       mem_rd_wr;

clocking cb@(posedge clock);
     default input #1 output #1;
     output     mem_data;
     output      mem_add;
     output mem_en;
     output mem_rd_wr;
endclocking

modport MEM(import cb.*,input clock);

endinterface
////////////////////////////////////////////////

In this interface, I need to modify the parameter of modport. The keyword import cb.* cause an error in the simulator. I have to replace import cb.* for clocking cb:

Modified code to run in the "irun":   modport MEM(clocking cb,input clock);

//mem_interface mem_intf(Clock); original interface;

To access any signal from interface, I have to modify the access way for each signal. For instance:
original code: mem_intf.mem_rd_wr <= 0;
to:             mem_intf.cb.mem_rd_wr <= 0; // I have to use ".cb." to access the internal signal of interface.

*******************************
*******************************
-------Example 2:
I could not instanciate an array of interfaces. The original code, the constructor "new" has an parameter that is
an array of interfaces (virtual output_interface.OP output_intf_new[4]). However, the irun rised an error.

original code:

function new(virtual mem_interface.MEM    mem_intf_new       ,
             virtual input_interface.IP input_intf_new     ,
             virtual output_interface.OP output_intf_new[4] );

this.mem_intf      = mem_intf_new    ;
this.input_intf    = input_intf_new ;
this.output_intf   = output_intf_new ;

endfunction : new

/////////////////////////////////////////////////////

Code modified: (this code works well)...
/////////////////////////////////////////////////////
class foo;
//virtual output_interface.OP output_intf[3:0] ;

virtual output_interface.OP output_intf_3 ;
virtual output_interface.OP output_intf_2 ;
virtual output_interface.OP output_intf_1 ;
virtual output_interface.OP output_intf_0 ;

function new(virtual mem_interface.MEM    mem_intf_new       ,
             virtual input_interface.IP input_intf_new     ,
             virtual output_interface.OP output_intf_new_3,
             virtual output_interface.OP output_intf_new_2,
             virtual output_interface.OP output_intf_new_1,
             virtual output_interface.OP output_intf_new_0);

this.mem_intf      = mem_intf_new    ;
this.input_intf    = input_intf_new ;

this.output_intf_3   = output_intf_new_3;
this.output_intf_2   = output_intf_new_2;
this.output_intf_1   = output_intf_new_1;
this.output_intf_0   = output_intf_new_0;

endfunction : new
///////////////////////////////////////////////////

I must instanciate four interfaces separately, because the constraint imposed by irun simulator.

*******************************
*******************************
Example 3: ////////////////////////////////////////////////////////////////////////////
class Packet;
...
rand byte data[;

----- >>constraint solve_size_length { solve data.size() before length; } << ------
...
This example does not work. I tried to use data.size and the "solve ... before" construction does not work. "irun" has generated an syntax error.
What the suitable manner to use solve and before constructions using data.size?

*******************************
*******************************
------Example 4: //////////////////////////////////////////////////////////////
The example 4 presents the most important issue in this mail. See the function called "byte_pack" below the constraints in the Packet class.
This function has as parameter a dynamic array passed by reference.
The "bytes" dynamic array is a stream of bytes from a packet.
These fields are packed in this stream. However, when this function is performed, several results seem unpredictable.
As example of this behaviour is that fields length,da and sa are modified, violating the constraints (ex: this constraint length_kind == GOOD_LENGTH) -> length == data.size();
happens rarely. )
When the function byte_pack is not performed (I commented it), all the constrains are meet.
The question is : how can I passed a array by reference? Is it possible in the cadence systemverilog simulator implamentation?

/////////////////////////////////////////////////////////////////////////
class Packet;
rand fcs_kind_t     fcs_kind;
rand length_kind_t length_kind;

rand bit [7:0] length;
rand bit [7:0] da;
rand bit [7:0] sa;
rand byte data[;//Payload using Dynamic array,size is generated on the fly
rand byte fcs;

constraint address_c { da inside {`P0,`P1,`P2,`P3} ; }

constraint payload_size_c { data.size() inside { [1 : 255]};}

constraint length_kind_c {
   (length_kind == GOOD_LENGTH) -> length == data.size();
   (length_kind == BAD_LENGTH) -> length == data.size() + 2 ; }


constraint fcs_kind_c {
   (fcs_kind == GOOD_FCS) -> fcs == 8'b0;
   (fcs_kind == BAD_FCS) -> fcs == 8'b1; }

virtual function int unsigned byte_pack( ref logic [7:0] bytes[);
bytes = new[data.size() + 4];
bytes[0] = da;
bytes[1] = sa;
bytes[2] = length;
foreach(data[i])
bytes[3 + i] = data[i];
bytes[data.size() + 3] = cal_fcs();
byte_pack = bytes.size();
endfunction : byte_pack
///////////////////////////////////////////////////////////////////////

Besides of that issues I mentioned, I am also writing this mail to know more about further versions of SystemVerilog simulator implementations will aggregate the all standard issues from Systemverilog.

I apologize for long text.

Thank you in advance.

Eduardo Wenzel Brião, PhD
Verification Engineer - CEITEC S.A. -
Porto Alegre, RS, Brazil