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 e-code: DLX VLIW modeling and test generation 

Last post Wed, Jan 6 2010 7:41 PM by srinicvc. 1 replies.
Started by archive 05 Feb 2006 12:20 PM. Topic has 1 replies and 16765 views
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  • Sun, Feb 5 2006 12:20 PM

    • archive
    • Top 75 Contributor
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    e-code: DLX VLIW modeling and test generation Reply

    This shareware package contains an environment for functional test
    generation for a modified version of the VLIW DLX architecture
    using Verisity Specman Elite.

    The implementation is a modified version of the DLX architecture. It has five stages: Fetch, Decode, Execute, Memory, and Writeback. The Execute stage has four parallel paths: integer ALU, four-stage floating-point adder(FADD), seven-stage multiplier (MUL), and a multi-cycle divider (DIV).

    Please see more details in the package README file.

    This shareware was contributed by Prabhat Mishra, University of California, Irvine. The work was supported by the Verisity University Program.

    Author: Yaron Kashai updated 5/10/2004 42163 bytes


    Originally posted in cdnusers.org by Administrator
    • Post Points: 20
  • Wed, Jan 6 2010 7:41 PM

    • srinicvc
    • Not Ranked
    • Joined on Tue, Nov 17 2009
    • Bangalore, Karnataka
    • Posts 5
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    Re: e-code: DLX VLIW modeling and test generation Reply

    Hello,

      I tried downloading it (after logging in to the forum with valid UID & password), I get some 48KB file, but when trying to open the WinZIP complains it is corrupted/damaged. Does anyone have a better link please?

     

    Thanks

    Srini

    www.cvcblr.com

    Srinivasan Venkataramanan Chief Technology Officer CVC pvt. Ltd. www.cvcblr.com Bangalore, India
    • Post Points: 5
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Started by archive at 05 Feb 2006 12:20 PM. Topic has 1 replies.