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 simulation only 0/1 

Last post Wed, Jun 4 2008 11:16 PM by archive. 1 replies.
Started by archive 04 Jun 2008 11:16 PM. Topic has 1 replies and 3184 views
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  • Wed, Jun 4 2008 11:16 PM

    • archive
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    simulation only 0/1 Reply

    Hi,

        Do anyone know if there is a plusarg which can make NC to simulation signal only have two state 0/1 instead of four state 0/1/x/z.  I wan't to speed up the simulation I wan't to if there is a way.

    Thanks!


    Originally posted in cdnusers.org by huyong
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  • Thu, Jun 5 2008 9:59 AM

    • archive
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    RE: simulation only 0/1 Reply

    I don't know of such a switch. However, I don't think the overhead in speed would be that noticable. I would think it would help more with memory. One way to check it out would be to use the SystemVerilog type of 'bit' instead of 'reg'.

    Tim


    Originally posted in cdnusers.org by tpylant
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Started by archive at 04 Jun 2008 11:16 PM. Topic has 1 replies.