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 vhdl-verilog interoperation ? 

Last post Wed, Dec 17 2008 1:27 PM by Mickey. 6 replies.
Started by archive 07 Feb 2007 10:25 AM. Topic has 6 replies and 4372 views
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  • Wed, Feb 7 2007 10:25 AM

    • archive
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    vhdl-verilog interoperation ? Reply

    Can I force or probe a signal in vhdl module from verilog top testbench?
    I heard some simulator has its own way to do that easily, can you give me a example to do that with ncsim?

     


    Originally posted in cdnusers.org by hubertx
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  • Wed, Feb 7 2007 12:28 PM

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    RE: vhdl-verilog interoperation ? Reply

    Some of the more recent versions of IUS (ncsim) will take '.' as the hierarchical separator through a mixed language hierarchy. In older versions, you would have to guess at when to use '.' and ':' through a hierarchical reference.

    If you're not sure, bring up the design browser and scope down into the module you are interested in and the design browser will show you the hierarchical path with the appropriate delimiters.

    Let us know if this doesn't answer your question.

    Harlin!


    Originally posted in cdnusers.org by Harlinator
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  • Fri, Feb 9 2007 9:28 AM

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    RE: vhdl-verilog interoperation ? Reply

    The testbench is verilog and the design is VHDL. So we instantiate the VHDL design (em0) at the verilog top level and force signals as follows:

    signal -force em0__ec0__fp0__flport_1__secnt_mclr 0
    (this is for the Palladium)

    hope that helps!


    Originally posted in cdnusers.org by tom paulson
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  • Fri, Feb 9 2007 10:25 AM

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    RE: vhdl-verilog interoperation ? Reply

    Hey, Tom!

    Also, in Palladium, once it goes through design import, there's no language difference (in reality, after HDLICE it's generally all verilog netlists). You can set the delimiterRule to verilog and then use '.' as hierarchical delimiter for the entire design. Using '.' is even more advantageous when you start with a gate-level netlist that usually contains instance names like '\a.b.c.d[0]_456' or the like. Those things get ugly real fast.

    Harlin!


    Originally posted in cdnusers.org by Harlinator
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  • Fri, Feb 9 2007 10:30 AM

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    RE: vhdl-verilog interoperation ? Reply

    hey Harlin...we have used VHDL for so long we just haven't changed. When we evaluated assertions on the Palladium, we did use the "." as the separator...thanks!


    Originally posted in cdnusers.org by tom paulson
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  • Tue, Dec 16 2008 8:17 PM

    • MSRajan
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    Re: RE: vhdl-verilog interoperation ? Reply

    Hi,

    I am using ncsim, Could you please tell me what is the syntax for forcing vhdl (RTL) signal from verilog testbench.

     Thanks.

     

    Regards,

    Rajan 

     

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  • Wed, Dec 17 2008 1:27 PM

    • Mickey
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    Re: RE: vhdl-verilog interoperation ? Reply

     Hi Rajan,

    I am assuming that you are attempting to create the force by directly assigning a value to the signal using an out-of-module reference (OOMR) path from within a verilog procedural block.  As you've probably discovered there is no way to do the above in verilog code using an OOMR.  This is because any OOMR path that begins with a verilog instance must end in a verilog instance.  That's not to say, however, that it can't be done, it just can't be done within the verilog coding.

    The way to do this is by using the tcl interface to ncsim.  Be aware that you will also need to insure that you have elaborated the design with write access.  The tcl argument to execute the force is as follows, depending on whether the signal is one or multiple bits: 

    force path.to.the.signal = '0'

    force path.to.the.vector = "1001101"

    Hope that helps.

    Mickey

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Started by archive at 07 Feb 2007 10:25 AM. Topic has 6 replies.