I checked with one of our VLE/APD design experts, and he suggested the following:
Tools Needed: Composer (Create IC or SiP designs), VLE (IC layout), SiP Layout and ADE (Virtuoso Analog Design Environment): Glue of IC and SiP tools available using SiP RF Architect
1. Export the DIE from VLE that creates a Composer symbol and SiP footprint for Allegro Package Design tool
2. Use above generated SiP symbol (Composer) and footprint (SiP layout) in SiP design
3. Add package to the die(s) in SiP Layout and extract parasitics using solvers.
4. Back-annotate this extracted model (and critical Package routes) back to SiP design schematic (Composer)
5. Use ADE to simulate Composer SiP design together with IC DIE and Package parasitics -- ADE is Composer integrated with Spectre and other simulators.
- Calibre extracted IC parasitics would be simulatable in ADE
6. Capabilities like design of off-chip components, partial circuit extraction for simulation, MTS would augment the solution
Originally posted in cdnusers.org by BillAcito