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 LVS and "selfmade" mosfet layout in VXL 

Last post Mon, Oct 9 2006 1:34 AM by archive. 2 replies.
Started by archive 09 Oct 2006 01:34 AM. Topic has 2 replies and 2303 views
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  • Mon, Oct 9 2006 1:34 AM

    • archive
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    LVS and "selfmade" mosfet layout in VXL Reply

    Hello,

    a question from a Cadence beginner:

    • I have a simple NAND schematic. This schematic uses pcell mosfets for circuit simulation.
    • Now I want to design my own layout for this schematic using Virtuoso XL layout editor
    The problem is:
    In my case I want to design the mosfets by hand, not using the prebuild / automatically generated pcell layouts from the library.

    When I'm designing my mosfet by hand in VXL, the program highlights the DIFF/Poly crossing (channel) to indicate an error. I'm not really sure why, but it seems as if the program is not able to find a corresponding channel in the schematic and the highlighted error indicates a mismatch between schematic and layout.
    A DRC doesn't report any errors and the mosfet's width & length is exactly matching the values of the corresponding transistor in the schematic - so the "selfmade" layout of the mosfet is definitly ok.

    Another way I tried is placing a mosfet pcell from the library and flattening it's hierarchy to optimize it's structure (for example the adjustment of the location and the number of source / drain contacts). But as soon as I flatten the hierarchy of the pcell, VXL looses the "connection" between pcell in schematic and it's corresponding (now flattened) layout. Again the DIFF/Poly crossing gets highlighted.

    The main problem is that a LVS run now results in missing instances and unknown nets in layout although they are there. The LVS doesn't seem to recognize the correspondance between "selfmade" layout parts and instances in the schematic.

    The strange thing I recognized is, that prebuild digital standard cells pass the LVS without any errors - although they are also made up of a schematic using prebuild pcells and a selfmade layout without the use of those pcells...

    I hope the problem description is understandable...

    So finally my question is:
    Is it possible to tell VXL something like: "Those parts in the layout window correspond to instance XYZ in the schematic"? This would at least prevent the LVS from reporting missing instances in layout.

    Thanks for any answer / help on this subject!



    Originally posted in cdnusers.org by designer
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  • Sun, Oct 15 2006 11:34 PM

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    RE: LVS and "selfmade" mosfet layout in VXL Reply

    It is difficult to debug this issue without seeing the specific testcase but the following pointers may help to resolve the problem



    You mention that the “program highlights the DIFF/Poly crossing (channel) to indicate an error” - I can’t say for sure why you are seeing an error here but by using Markers-Explain you can query the problem and this may help to explain what the issue is. Check against source could also be run to find differences between the schematic and layout. Xprobe can be used too check the connectivity.



    I don’t think that flattening the hierarchy is the solution here. It would be better to create the layout instances to correspond directly to the schematic instances because in VXL we are not able to create correspondance with *shapes*, only with nets and instances. If the instance names match between the schematic and layout the correspondence will be created automatically, if not then this can be achieved by using Create Device Correspondence and Updated Device Correspondence commands. Full details of these commands are available in Chapter 12 of the Virtuoso XL Layout Editor User Guide. It can also be achieved by adding an lxUseCell property on the instances in the schematic; again this is documented in the user guide


    Originally posted in cdnusers.org by Alexc
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  • Wed, Oct 18 2006 4:58 AM

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    RE: LVS and "selfmade" mosfet layout in VXL Reply

    Hi Alexc,

    thanks for your response!

    > because in VXL we are not able to create correspondance with *shapes*, only with nets
    > and instances

    In my case this feature would be very helpfull. I have an existing layout without instances (only *shapes*) that must be redrawn with different scale of the transistors. As the layout is quite complicated and optimized by hand, I can't simply replace the existing transistors with "new" instances as it is simply not possible to generate exactly the look and feel I need in my specific case. By now my approach is scaling the whole layout, adjust some parts not to be scaled (e.g. contacts) and that's it. Everything works fine except VXL not recognizing the transistor instances. Therefore I was searching for a feature like "take shape 1,2 and 3" and tell VXL "this is now instance XYZ".

    Nevertheless all this stuff isn't as important
    any more as it was one week ago. I at least convinced the LVS Checker to automatically detect my handmade transistors and find the corresponding ones in schematic. As I am a really stupid boy, I forgot to paint an additional layer to signal thicker oxide that is part of the transistors/instances in schematic and simply does not exist in the old layout with thin oxide I used as pattern. The LVS Checker didn't find the schematic instances in layout because of the layer difference between schematic and layout. Now that I added the thick oxide layer LVS works fine and that was all I wanted for now.

    Thanks again for your help!


    Originally posted in cdnusers.org by designer
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Started by archive at 09 Oct 2006 01:34 AM. Topic has 2 replies.