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 verilog netlist simulation 

Last post Fri, Jul 11 2014 2:32 AM by KUMARJAYA. 0 replies.
Started by KUMARJAYA 11 Jul 2014 02:32 AM. Topic has 0 replies and 75 views
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  • Fri, Jul 11 2014 2:32 AM

    • KUMARJAYA
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    • Joined on Sat, Sep 14 2013
    • Posts 4
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    verilog netlist simulation Reply

    is it possible to interconnect analog and digital modules in cadence virtuoso?if possible which simulator need to use(AMS or SPECTRE VERILOG)?

    If i am using only verilog netlist simulation in vituoso then which simulator need to use?

    For verilog simulation is it possible to give inputs by voltage source ?

     

     

    please help me......... 

     

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    • Post Points: 5
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Started by KUMARJAYA at 11 Jul 2014 02:32 AM. Topic has 0 replies.