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 mixed signal simulation 

Last post Tue, Jul 29 2014 2:38 AM by Andrew Beckett. 3 replies.
Started by KUMARJAYA 09 Jul 2014 04:08 AM. Topic has 3 replies and 487 views
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  • Wed, Jul 9 2014 4:08 AM

    • KUMARJAYA
    • Not Ranked
    • Joined on Sat, Sep 14 2013
    • Posts 4
    • Points 65
    mixed signal simulation Reply
    is it possible to simulate verilog netlist in cadence virtuoso?how to bind the standard netlist cell to the corresponding code?
    • Post Points: 20
  • Mon, Jul 14 2014 5:38 AM

    Re: mixed signal simulation Reply

    There's a tutorial in the installation, and covered in the AMS documentation. 

    In the CIW, do Help->Virtuoso Documentation. In the Documentation Browser (left pane of the help system) expand IC6.16 (or similar), AMS Environment and then Virtuoso AMS Designer Environment Tutorials. This tells you where to find various tutorials on getting started with AMS Designer.

    Regards,

    Andrew.

    • Post Points: 20
  • Thu, Jul 17 2014 7:32 AM

    • KUMARJAYA
    • Not Ranked
    • Joined on Sat, Sep 14 2013
    • Posts 4
    • Points 65
    Re: mixed signal simulation Reply

    thanks for your valuable guidance....

    sir,

    in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks.

    so i generate verilog netlist of the corresponding digital block.

    But after integrating it with analog block i need to check functional and transistor level behavior of corresponding standard cells in verilog netlist.

    is verilog or VHDL AMS as standard cell for verilog netlist ?

    if not please give some solution for it........  

     

      

    • Post Points: 20
  • Tue, Jul 29 2014 2:38 AM

    Re: mixed signal simulation Reply

    That's exactly what AMS is for - you can have Verilog or VHDL or System Verilog or VerilogAMS or VHDL AMS descriptions of your blocks and simulate them in conjunction with pure analog parts (transistor level, or VerilogA). Standard cells would normally have either a Verilog or VHDL description (Verilog more commonly). 

    This is the kind of thing that the tutorial will show you how to use the hierarchy editor to pick appropriate views of each cell, and then simulate everything together.

    Unfortunately your question is extremely open ended (and not very clear) so it's hard to give a precise answer to a vague question...

    Regards,

    Andrew.

    • Post Points: 5
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Started by KUMARJAYA at 09 Jul 2014 04:08 AM. Topic has 3 replies.