Home > Community > Forums > Digital Implementation > sub threshold leakage power analysis and optimization

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 sub threshold leakage power analysis and optimization 

Last post Mon, Jul 7 2014 9:54 PM by amuidhay. 0 replies.
Started by amuidhay 07 Jul 2014 09:54 PM. Topic has 0 replies and 577 views
Page 1 of 1 (1 items)
Sort Posts:
  • Mon, Jul 7 2014 9:54 PM

    • amuidhay
    • Not Ranked
    • Joined on Thu, Jul 3 2014
    • Posts 1
    • Points 5
    sub threshold leakage power analysis and optimization Reply

    Hi,

    Im very new to cadence. Is it possible to analyse leakage power in low digital circuits at circuit level? what is the difference between leakage power analysis at circuit level and at logic level? which tool is used to do so? I dont know how to..where to start with? My aim is to take tablet PC as a reference..and minimize sub threshold leakage power particularly in digital circuits of tablet PC architecture... results in reduction of its static power dissipation.

    It would be very useful if i get any quick response. Thanks. 

    • Post Points: 5
Page 1 of 1 (1 items)
Sort Posts:
Started by amuidhay at 07 Jul 2014 09:54 PM. Topic has 0 replies.