I have a question regarding the use of non-clock tree cells on clock tree paths.
The netlist post-synthesis that I have, contains standard muxes and gating-elements on clock paths.
During the P&R clock-tree-synthesis step, clock tree buffers are inserted but the standard muxes and gating elements are not swapped to their "clock cell" version.
I have 2 questions:
1/ Is there a way to force "RTL compiler" tool to use only clock cells on clock tree paths when synthesizing the netlist?
2/ Is there a way to force "Encounter" tool to swap the non-clock-cells on clock paths to their "clock cell" version during clock tree synthesis step? I mean is there a way to fully resynthesize the clock paths with clock tree cells?
Thanks in advance for your help.