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 Verilog In: Missing `define directives 

Last post Tue, Jun 3 2014 2:57 PM by dbankman. 0 replies.
Started by dbankman 03 Jun 2014 02:57 PM. Topic has 0 replies and 1938 views
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  • Tue, Jun 3 2014 2:57 PM

    • dbankman
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    • Stanford, CA
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    Verilog In: Missing `define directives Reply

    I'm trying to import a verilog file containing multiple cell modules. Verilog In imports each cell module as a functional view in the appropriate cell, but the necessary `define directives from within a cell module are missing.

     For example, a cell module in this file looks like:

     `celldefine

    `define EXAMPLE 1

    module ...

    ...(`EXAMPLE is used)...

    endmodule

    `endcelldefine

    The imported functional view contains the lines where `EXAMPLE appears, however, its `define statement is missing.

    Is there an option for retaining the `define statements in the imported functional view?

    Thanks

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    • Post Points: 5
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Started by dbankman at 03 Jun 2014 02:57 PM. Topic has 0 replies.