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 How to force a small gate structure during RTL Compiler synthesis? 

Last post Thu, Apr 24 2014 11:09 AM by rexnyu. 0 replies.
Started by rexnyu 24 Apr 2014 11:09 AM. Topic has 0 replies and 2925 views
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  • Thu, Apr 24 2014 11:09 AM

    • rexnyu
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    • Joined on Tue, Mar 26 2013
    • Posts 15
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    How to force a small gate structure during RTL Compiler synthesis? Reply

     In my verilog code, I have XOR1 gate (in0, in1, out). Port "out" connects to the "D" input of a DFF. A code sample is below:

    assign out = in0 ^ in1;
    dff dff_0(.CLK(CLK), .in(out), .out(q));
    ..................
    module dff(CLK, in, out);
        input CLK;
        input [127:0] in;
        output reg [127:0] out;
    
        always@(posedge CLK)
            out <= in;
    
    endmodule
    

    However, after synthesis one additional XOR2 gate is inserted between XOR1 and DFF, i.e., "out" connects to one input of XOR2 and the output of XOR2 connects to "D" input of the DFF. I understand that the tool is doing some optimization related to my other logic. But how can I enforce the gate sequence in my verilog code in this specific case? (XOR1 connect to DFF directly) I am fine with restructuring the code.

    BTW: I do not use any timing constraints.

    • Post Points: 5
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Started by rexnyu at 24 Apr 2014 11:09 AM. Topic has 0 replies.