Home > Community > Forums > Custom IC Design > veriloga capacitor model

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 veriloga capacitor model 

Last post Mon, Dec 3 2007 6:32 PM by archive. 1 replies.
Started by archive 03 Dec 2007 06:32 PM. Topic has 1 replies and 1486 views
Page 1 of 1 (2 items)
Sort Posts:
  • Mon, Dec 3 2007 6:32 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,950
    veriloga capacitor model Reply

    hi,

    i have defined a capacitor using the following statement v(p,n)<+ C*ddt(V(p,n)) in veriloga. I found that this does model the behavior of a capacitor but the spectre simulator doesnt recognize this as a physical capacitor at that node. (It doesnt show the capacitance value in captab).  Is there some other way of modeling a capacitor

    thanks,
    Anisha


    Originally posted in cdnusers.org by anisha_r
    • Post Points: 0
  • Mon, Dec 3 2007 9:26 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,950
    RE: veriloga capacitor model Reply

    Probably you should report this to customer support - I suspect we need to add some support for an attribute so that the expression can be identified as being a capacitor.

    As a workaround, you could instantiate a primitive capacitor using a structural instantiation within the Verilog-A. i..e

    capacitor #(.c(C)) C1(p,n);

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
    • Post Points: 0
Page 1 of 1 (2 items)
Sort Posts:
Started by archive at 03 Dec 2007 06:32 PM. Topic has 1 replies.