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 Syntax V93 VHDL  

Last post Mon, Jan 13 2014 9:22 AM by tonio. 0 replies.
Started by tonio 13 Jan 2014 09:22 AM. Topic has 0 replies and 4253 views
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  • Mon, Jan 13 2014 9:22 AM

    • tonio
    • Not Ranked
    • Joined on Wed, Aug 28 2013
    • York, Yorkshire
    • Posts 8
    • Points 115
    Syntax V93 VHDL Reply

     Hi there,

     

    I am building an ip, i tested it on Xilinx FPGA is seems works 

     

    now i m testing it on virtuoso cadence and give me this 2 errors, someone can help please 

    1) -------------------------------------

    E,MLTDRV (./test.vhdl,17|0): Signal/register 'M_ADDR' has multiple drivers.
    ------
    The specified signal/register has multiple drivers which can
    be active simultaneously. This may lead to signal/register
    having undefined/unexpected value and can also result in
    difference in simulation and synthesis behavior.

    The following parameter present in the default rules file can be used to modify the behavior of this check:
    params MLTDRV {ignore_z_drivers="yes|no"}

    The default value of this parameter is 'yes'. In this case, if a signal has two drivers with
    one of the drivers being 'Z', the tool will allow the signal to have a 'Z' driver and a
    violation will not be reported. Alternatively, when this parameter is set to 'no', the 'Z' driver
    will be considered invalid and a violation will be reported.

    The following example illustrates the occurrence of MLTDRV:
    assign sig_a = var_a;
    assign sig_a = var_b;

    In the above example, 'sig_a' is multiply driven.

    Line 17---  M_ADDR :   OUT std_logic_vector(31 DOWNTO 0);

    Line 378---M_ADDR <= std_logic_vector(to_unsigned(1, 32))+ u2fpi; 

     

    2)-------------------------------------------------------

    *E,MLTDRV (./test.vhdl,19|0): Signal/register 'M_RD' has multiple drivers.
    ------
    The specified signal/register has multiple drivers which can
    be active simultaneously. This may lead to signal/register
    having undefined/unexpected value and can also result in
    difference in simulation and synthesis behavior.

    The following parameter present in the default rules file can be used to modify the behavior of this check:
    params MLTDRV {ignore_z_drivers="yes|no"}

    The default value of this parameter is 'yes'. In this case, if a signal has two drivers with
    one of the drivers being 'Z', the tool will allow the signal to have a 'Z' driver and a
    violation will not be reported. Alternatively, when this parameter is set to 'no', the 'Z' driver
    will be considered invalid and a violation will be reported.

    The following example illustrates the occurrence of MLTDRV:
    assign sig_a = var_a;
    assign sig_a = var_b;

    In the above example, 'sig_a' is multiply driven.

     

    line 19 ----- M_RD  : INOUT std_logic;

    line 493 --- M_ADDR <= std_logic_vector(to_unsigned(0,32))+u3fpi;

     

    Thank  you so much for your help regards 

     

     

     

     

     

    • Post Points: 5
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Started by tonio at 13 Jan 2014 09:22 AM. Topic has 0 replies.