Yes original post had simpleer example, I deleted it, then put this example where all top ports are different to better udnerstand situation.
You was actually right about verilog port order, in fact I was suspecting that too before, but since it didnt matter because of [ <> issues I thought its not verilog order which matters. Only when I managed to get it working after changing <> to [ during netlisting and after arranging my ports in CDF termOrder I discovered now that they match the way how they appear in verilog!
Here is the description of top instance from verilog:
module refleks_switcher (
If you look again at the working final netlist from my previous post, you will see that it matches the verilog port order shown above!
So, turns out, that in order to get it working, one just needs to create auCdl and symbol views which are same, go to CDF properties and arrange the termOrder in a way in which it appears in the top verilog cell in verilog source.
Then in LVS, just put in three files: top verilog source, CDL description of standard cells and final CDL netlisting of top structure.
And yes, <> vs [ matters! I verified it! If I do not use an option to change <> to [ during netlisting the LVS goes banana.
The only weird downside is, as I described before, after Netlisting with <> to [ change option, the exclamation mark "!" is removed after all GND and VDD ports, so I have to go ahead and add them, but its kinda ok, I can live with it so far, at least things are working as they "supposed" to.
p.s. also had to add *.RESI to final netlist because of those cds_thru things. And yes, I will use auCdl and symbol views which have same content from now on. Also, I control CDF bus ordering with "D" property set up in .simrc.
OK, finally, digital placing/autorouting with further integration in Virtuoso without involving schematics is achieved.