I want to check interconnectivity among several IP blocks(in VHDL and Verilog) with PSL vunits. However I have a problem in binding. As I understand, i can bind the vunit to only one entity. But for interconnect check, I need port signals from both entities(IPs) so that I can continiously compare them. I can achieve this with SVA using SystemVerilog interfaces, but in PSL I am stuck.
Thanks for your help in advance,