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 VDD VSS open violations on FULL CHIP boundary 

Last post Fri, Oct 18 2013 10:05 PM by vimalraj205. 1 replies.
Started by bharat kurra 18 Oct 2013 01:53 AM. Topic has 1 replies and 3632 views
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  • Fri, Oct 18 2013 1:53 AM

    • bharat kurra
    • Not Ranked
    • Joined on Tue, Jun 22 2010
    • hyd, Andhra Pradesh
    • Posts 14
    • Points 365
    VDD VSS open violations on FULL CHIP boundary Reply

    Hi All,

     

    I see VDD VSS open violations for full chip boundary  . I have done my powerplan correctly and specified all he global nets

    but i still open vioaltion on the full chip boundary

    I feel these has false vioaltions , please help me on this

    verify connectivity summary  

     Begin Summary 

        18 Problem(s) (ENCVFC-200): Special Wires: Pieces of the net are not connected together.

        49 Problem(s) (ENCVFC-92): Pieces of the net are not connected together.

        67 total info(s) created.

    End Summary

     

    Thanks in Advvance

     

    Regards

    -Bharath 

    • Post Points: 20
  • Fri, Oct 18 2013 10:05 PM

    • vimalraj205
    • Not Ranked
    • Joined on Wed, Feb 6 2013
    • tuticorin, Tamil Nadu
    • Posts 6
    • Points 65
    Re: VDD VSS open violations on FULL CHIP boundary Reply

    Hai friend

    Have you given the global net connections correctly and also the options given for the follow pins

    can you please give a pictorial view of your design......

    thanks,

    Vimal.

     

     

    • Post Points: 5
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Started by bharat kurra at 18 Oct 2013 01:53 AM. Topic has 1 replies.