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 Ultrasim Verilog simulation with ncvlog 

Last post Mon, Oct 14 2013 3:27 PM by Bardia B. 5 replies.
Started by Bardia B 14 Oct 2013 11:52 AM. Topic has 5 replies and 2367 views
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  • Mon, Oct 14 2013 11:52 AM

    • Bardia B
    • Not Ranked
    • Joined on Mon, Jan 3 2011
    • Posts 7
    • Points 95
    Ultrasim Verilog simulation with ncvlog Reply

    I have a problem with Ultraim Verilog. The problem is that my verilog code is not supported by verilog -XL and gives error.

    I was wondering if there is anyway to  use nc-vlog instead of Verilog -XL during ultrasim verilog simulation?

     Thank you,

    Bardia 

    • Post Points: 20
  • Mon, Oct 14 2013 12:39 PM

    Re: Ultrasim Verilog simulation with ncvlog Reply

    You should use "ams" (AMS Designer) as the simulator. SpectreVerilog and UltrasimVerilog are obsolete technology and have been for many years. 

    Regards,

    Andrew 

    • Post Points: 20
  • Mon, Oct 14 2013 1:08 PM

    • Bardia B
    • Not Ranked
    • Joined on Mon, Jan 3 2011
    • Posts 7
    • Points 95
    Re: Ultrasim Verilog simulation with ncvlog Reply
    Thanks Andrew for your quick reply. The problem with AMS is that I cannot use ultrasim for transient analysis using AMS. It uses only spectre for transient analysis. I don't know if this is the case only with my Cadence or it is always like this. Ultasim option is only provided for envelope detection. I would like to use ultrasim transient analysis in order to be able to do faster transient simulations. please correct me if I am wrong.
    • Post Points: 20
  • Mon, Oct 14 2013 1:14 PM

    Re: Ultrasim Verilog simulation with ncvlog Reply

    Er, no. You can use ultrasim as the solver for transient sims too. Did you try just setting Simulation->solver and setting it to Ultrasim?

    Ultrasim has been supported with AMS for years and years, and always for transient.

    Regards,

    Andrew 

    • Post Points: 20
  • Mon, Oct 14 2013 1:31 PM

    • Bardia B
    • Not Ranked
    • Joined on Mon, Jan 3 2011
    • Posts 7
    • Points 95
    Re: Ultrasim Verilog simulation with ncvlog Reply
    OMG! what a rookie mistake! Thanks a lot for your help Anderw. I didn't know that option (solver) exists at all.

    So when i choose the ultrasim in solver, the conservative/moderate/liberal option will be ignored? (accuracy options during enabling the transient analysis)

    also I get an error like this when I run the simulation:

    No connection module found: Need an input port of discrete discipline logic, and an output port of continuous discipline electrical.

    Do i need to insert a connection betwenn digital (verilog) module and analog part to convert logic levels to voltage level, right? where I can find this connection module?

    Sorry if these are very basic  questions. But this is the first time I am running mixed-mode simulation. I would appreciate if you can introduce a good tutorial or user guide for this.

    Thanks again,
    Bardia.
    • Post Points: 5
  • Mon, Oct 14 2013 3:27 PM

    • Bardia B
    • Not Ranked
    • Joined on Mon, Jan 3 2011
    • Posts 7
    • Points 95
    Re: Ultrasim Verilog simulation with ncvlog Reply

    The problem is solved and the ams designer is running perfectly.

     Thanks for your help Andrew. 

     

    • Post Points: 5
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Started by Bardia B at 14 Oct 2013 11:52 AM. Topic has 5 replies.