Hi, cadence virtuoso schematic editor L (615) users:
How to tie two global signals together so that when netlist there is only one global signal name for both cases.
For example, in my design all digital parts have ground vss! and all analog parts have ground vssa!. Since the design only has one ground pin VSS, I need to tie vss! and vssa! together to the pin VSS. This way I will not have ant LVS problem.
I tried to do this (put symbol vss and symbol vssa on the schematic page and tie them together to the pin VSS),
but after check and save, Cadence gave errors:
Error: Net "vss!" shorted to net "vssa!",
Error: Global signal "vss!" shorted to terminal "VSS".
Does anyone have similar issues? It looks like two global nets can not be tied together. Is it right?