Hello, Cadence community,
I'm designing an RF power amplifer (PA) and have stumbed on a problem. First of all, the PA has 2 stages - 1st stage is A class, 2nd stage - meant to be AB class. Output matching is precisely fixed to the required frequency.
The problem sound like this: I get a maximum amplitude of 400 mV at the gate of the output stage.Don't get me wrong, the input stage does it's work and amplifies the input signal to 2V p2p. But there is a 5-10 ohm stability resistor before the gate of the output stage and I guess that it is the bottleneck. Interstage matching is also included so that should not be the case.
As a result, my output stage is not in AB class mode (that's first of all) and the full potential is not achieved. Maybe that's the maximum I can achieve and if I want to increase the output power - the only way to do this is to increase the size of the output stage?
I'd appreciate any words of advice on this.