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 Classification of nets in DEF 

Last post Sun, Sep 22 2013 10:40 AM by fitz. 1 replies.
Started by RobB 20 Sep 2013 09:51 AM. Topic has 1 replies and 2331 views
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  • Fri, Sep 20 2013 9:51 AM

    • RobB
    • Not Ranked
    • Joined on Wed, Apr 29 2009
    • Fort Collins, CO
    • Posts 1
    • Points 20
    Classification of nets in DEF Reply

    Can anyone help me understand why there are classifications of NETS, PINS, and SPECIALNETS in DEF?

    I am looking at the Cadence 13.14 EDI LEF/DEF Language Reference manual - version 5.8, March 2013.

    It shows the following for NETS (and something very similar for PINS and SPECIALNETS) :


     NETS numNets ;

                 | TIEOFF}]


    And it has the following description:

    Specifies how the net is used. 
    Value: Specify one of the following:
    ANALOG Used as an analog signal net.
    CLOCK Used as a clock net.
    GROUND Used as a ground net.
    POWER Used as a power net.
    RESET Used as a reset net.
    SCAN Used as a scan net.
    SIGNAL Used as a digital signal net.
    TIEOFF Used as a tie-high or tie-low net.


    Having these classifications seems like a good idea (and they seem to be mentioned at least as far back as SOC8.1USR3's LEF/DEF Language Reference version 5.7 from June 2009). However, I don't know of any way to set, modify, or query them from within EDI.

    Is this possible? Thanks!

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    • Post Points: 20
  • Sun, Sep 22 2013 10:40 AM

    • fitz
    • Top 150 Contributor
    • Joined on Wed, Aug 4 2010
    • Kanata, Ontario
    • Posts 56
    • Points 745
    Re: Classification of nets in DEF Reply

     These basic NET attribute classifications are used to differentiate how EDI handles them during each of layout stages , placeDesign , clockDesign,  optDesign and routeDesign.

    The majority of the attributes are handled automatically for you by the standard flow.
    ie. The original create_clock constraint  tags the clk root for you and clockDesign tags the rest of the created tree for you.
    Then optDesign & RouteDesign  know not to disturb the sensitive clock tree placement or routes .

    ANALOG = custom manual route , "setAttribute -net -skip_routing true", to prevent routeDesign from automatically routing the specialNet.
    CLOCK = balanced "H" tree or mesh routing,  clockDesign generally automatically handles multiple clock attributes for you, getAttribute -net <clkNet>
    GROUND = "addRing & addStripe" router .
    POWER "addRing & addStripe" router.
    RESET "bufferTreeSynthesis" to buffer high fanout nets.
    SCAN defIn <top>.scanDef & scanTrace allows placeDesign to ignore and reorder scan chains  .
    SIGNAL <default> standard digital signal net .
    TIEOFF for some technologies  'b1/'b0 cannot attach directly to rails and require additional Pullup or pullDown cells

    The system is fairly straight forward until you step out of the standard flow and do something really funky with vi.

    • Post Points: 5
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Started by RobB at 20 Sep 2013 09:51 AM. Topic has 1 replies.