Home > Community > Forums > Custom IC Design > Error in sub-range ADC simulation.

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Error in sub-range ADC simulation. 

Last post Thu, Apr 19 2007 4:36 PM by archive. 3 replies.
Started by archive 19 Apr 2007 04:36 PM. Topic has 3 replies and 2016 views
Page 1 of 1 (4 items)
Sort Posts:
  • Thu, Apr 19 2007 4:36 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    Error in sub-range ADC simulation. Reply

    Hello.
    I am trying to simulate a 3bit ADC which incorporates sub ranging. Im using a swictched capacitor implementation of the circuit . There are 7 comparators used. these comparators are then used to select a given output of a DAC which is in actuality a thermometer code based DAC.
    The circuit schematic looks like the one in my attachment.

    When i try to simulate that, cadence flashes an error saying that
    "Only one connection to the following 7 nodes:"
    "The following branches form a loop of rigid branches (shorts) when added to the circuit:"

    Why is such an error flashed? In the case of my schematic, i do actually want a connection from those 7 nodes into the negative terminal of the op-amp.
    And what can be done to get rid of those errors and at the same time get that schematic implemented?

    Im including a gzipped version of the relevant lib. Please do have a look if that would help you understand the error better

    Best Regards,
    Aijaz


    Originally posted in cdnusers.org by aijazbaig1
    • Post Points: 0
  • Fri, Apr 20 2007 1:07 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Error in sub-range ADC simulation. Reply

    The loop of rigid branches is telling you that you have a set of voltage sources in parallel (which is obviously not valid). The single connection is not an issue - it's just the loop of rigid branches.

    Having looked, it's due to the instances of the switch models (dac_switch). The ahdl views for these look badly implemented to me.

    Note, you have written these using SpectreHDL which is no longer supported - in fact in the latest versions of spectre (MMSIM61) you cannot run it at all. You should be using Verilog-A instead. SpectreHDL was a precursor to VerilogA, and is now obsolete (the syntax
    is fairly similar though, so not hard to move to).

    I didn't try to correct the model because it is not that clear to me what you're actually trying to get the switches to do (plus the fact that you'll learn more in the process of fixing it). It may just be that they need some finite impedance, but I suspect it's just that they don't represent the right relationships.

    You might want to take a look at this book: http://www.designers-guide.org/Books/#Kundert-2004 . It's an excellent book on Verilog-A and Verilog-AMS.

    Best Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
    • Post Points: 0
  • Sat, Apr 21 2007 3:03 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Error in sub-range ADC simulation. Reply

    Thanks a lot for the tip andrew.
    Now that I have got the switch fixed, it does compiles properly. However, as in the case of most switched cap circuits, im having a lot of trouble with getting the circuit to converge.
    I have replaced the switch with a model which does have a finite ON resistance and a big OFF resistance. Heres what the code looks like:
    [code]
    // $Date: 1996/10/02 00:44:13 $
    // $Revision: 1.10 $
    //
    //
    //The sample SpectreHDL library is unsupported and subject to change
    //without notice. Future versions of SpectreHDL may not be compatible
    //with this library.
     
    //--------------------
    // sw
    //
    // -  switch
    //
    // vp,vn:        output terminals [V,A]
    // vctrlp,vctrln:     control terminals [V,A]
    //
    // INSTANCE parameters
    //    vth = threshold voltage [V]
    //
    // MODEL parameters
    //    {none}
    //
    // If ('vctrlp' - 'vctrln' > 'vth') then the branch between 'vp' and 'vn'
    // is shorted. Otherwise the branch between 'vp' and 'vn' is opened
    //

    module sw(vp, vn, vctrlp, vctrln) (vth)
    node [V,I] vp, vn, vctrlp, vctrln;
    parameter real vth;
    {
       enum {OPEN, CLOSED} sw_state;
       real Ron = 10;
       real Roff = 100M;
       
       analog {
          sw_state = (V(vctrlp,vctrln) > vth) ? CLOSED: OPEN;
        
          if ($threshold(V(vctrlp, vctrln) - vth, 1)){
    //      if ($threshold(V(vctrlp, vctrln) - vth, 1, $abstol("V"), 1.0)){
               sw_state = CLOSED;
          }

          if ($threshold(V(vctrlp, vctrln) - vth, -1)){
    //      if ($threshold(V(vctrlp, vctrln) - vth, -1, $abstol("V"), 1.0)){
               sw_state = OPEN;
          }

          if (sw_state == OPEN){
               V(vp,vn) <- Roff*I(vp,vn);
          }
          else{
               V(vp,vn) <- Ron*I(vp,vn);
          }
       }
    }
    [/code]
    As u can see, i modified the code of the sw from the ahdl library. Now (supposedly) it does always have a resistance between the two terminals.

    Nonetheless, I am facing convergence problems at some of the nodes and no matter what I try the warning doesn't seem to go.

    Heres the schematic
    And the simulation stops just after 1.25ns and it complains that the voltage/current changes at some nodes is just too much to take care of.
    As suggested in some of the places and app notes, i have tried attaching a LPF kind of a structure in the hope that it may prevent a sudden change in the voltage level. I tried adding big resistors from floating nodes to ground which took care of the problem of floating nodes.
    However, I do not understand how to prevent this sudden voltage change. will changing the value of ABSTOL or RELTOL make a difference. If yes then how do I do it?

    Additionally, is there anything in the circuit topology which causes it besides the obvious fact that many nodes are getting connected to a single node in the netlist. The only reasonable way I could think of to solve this was to insert nominal resistances in the path so as to prevent a short between these nodes in the schematic.

    As before id include the gzipped version of the relevant library. Please do have a look so you may find some factors which I may have overlooked.

    Best Regards,
    Aijaz


    Originally posted in cdnusers.org by aijazbaig1
    • Post Points: 0
  • Tue, Apr 24 2007 9:26 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Error in sub-range ADC simulation. Reply

    Hello.
    I have made my way out of the strange convergent errors and what I learned in a crude way was that sudden changes in voltages and currents need to be taken care of..
    I basically solved that problem using buffered inputs to nodes that were floating and added high impedance resistors to ground to floating nodes for some cases. Additionally modifying the cap values also made some effect. Furthermore I changed the switch model such that there always is a path between the input and output which toggles between high imp and low imp depending on the control input.

    additionally the way the chassis ground (floating ground) works for an op amp has always been a little mysterious to me. How does a VCVS model that effect of the two nodes being almost equipotential.

    Now a question regarding to my schematic (changed). As usual im including teh schematic so that it may become easy for u to comprehend what im sayin here.
    when the two capacitors switch states, some charge seems to be drawn from the floating ground which causes a very sharp voltage and consequently current spike at the outputs. I learned that it depends on the difference between the present value and the value it is supposed to get charged to plus the series resistance in its path such that it shudnt have allow an infinitely large current to flow through the circuit.
    But how does one get rid or reduce that problem in an op amp ckt in cadence?

    Additionally, with regards to the circuit, that circuit seems to be implementing a transfer function of
    [(C_s/C_f)*(V_in - V_Ref)] + V_Ref. I wonder whats causing it to hold a value of V_Ref causing it to add an unwanted DC offset.

    I am keen to know if the circuit topology is affecting the behavior in anyway..im dead sure it is..bt if anyone wud give me some hints to think of..it wud be great.

    Best Regards,
    Aijaz.


    Originally posted in cdnusers.org by aijazbaig1
    • Post Points: 0
Page 1 of 1 (4 items)
Sort Posts:
Started by archive at 19 Apr 2007 04:36 PM. Topic has 3 replies.