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Last post Mon, Sep 16 2013 6:58 AM by Andrew Beckett. 1 replies.
Started by Sayantan55 15 Sep 2013 09:20 AM. Topic has 1 replies and 4660 views
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  • Sun, Sep 15 2013 9:20 AM

    • Sayantan55
    • Not Ranked
    • Joined on Tue, Sep 18 2012
    • Posts 1
    • Points 20

    I am new to AMS language and design and I am trying to model an oscillator with the following features :  

    a. The oscillator operates at a default freq of say 32Khz, with tuning applicability from 20Khz to 50Khz.

    b. The oscillator operates in two power domains, one of 3.3v and other of 1.2v. 
    c. When the 1.2 v domain is off, the model latches the entire state of the oscillator and keeps oscillating in that state. Any new input provided at that time will have no effect.
    d. When the 3.3v domain is off, the model stops to oscillate and any latched state gets cleared.
    e. The model can have a fault mechanism, wherein, any out of range freq generated, sets a fault flag, that remains latched as an output high, until cleared externally. During this state, the oscillator block will generate the high freqeuncy but at the output, the clock will get blocked until fault gets cleared.


    Please can anybody here help me out with code snippets and guide me through the design ? Thanks in advance  

    • Post Points: 20
  • Mon, Sep 16 2013 6:58 AM


    You also sent me two personal messages on this. I will not answer any quicker if people do this. For a start, I'm actually out of the office for a few days, so I'm unlikely to be able to answer - and will not be any more able to answer if you send me personal messages!

    Your question is a bit "can you write this for me" - I would suggest a good place to start is by teaching yourself the language. A good book is The Designer's Guide to Verilog-AMS. There are also sample models in rfLib, ahdlLib, bmslib in the Virtuoso samples in the installation.



    • Post Points: 5
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Started by Sayantan55 at 15 Sep 2013 09:20 AM. Topic has 1 replies.