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 Verilog-AMS Bias Current Modelling 

Last post Wed, Sep 4 2013 6:52 AM by shalem7. 4 replies.
Started by shalem7 04 Sep 2013 02:51 AM. Topic has 4 replies and 5100 views
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  • Wed, Sep 4 2013 2:51 AM

    • shalem7
    • Not Ranked
    • Joined on Thu, Jan 19 2012
    • hyderabad, Andhra Pradesh
    • Posts 9
    • Points 120
    Verilog-AMS Bias Current Modelling Reply

    Hi All,

    I need to model a verilog-ams bias current model.

    I had coded in this way,

    I(out) <+ 1uA.

    In TB i put V(out) <+I(out)/R_LAOD.

    This worked fine at module level.

    Does this way of model works when the module connects with a SPICE block where the current is begin sinked.

    Is this the correct way to model the bias current in verilog AMS.

    Please provide your inputs to code the BIAS currents properly.

    Thanks,

    Shalem

    • Post Points: 20
  • Wed, Sep 4 2013 3:47 AM

    Re: Verilog-AMS Bias Current Modelling Reply

    Shalem,

    I don't think you've given enough details to go on, really. Please elaborate if you want an answer - I couldn't quite work out what you're asking (or even quite what you've implemented). Perhaps some pictures might help?

    Regards,

    Andrew.

    • Post Points: 20
  • Wed, Sep 4 2013 6:18 AM

    • shalem7
    • Not Ranked
    • Joined on Thu, Jan 19 2012
    • hyderabad, Andhra Pradesh
    • Posts 9
    • Points 120
    Re: Verilog-AMS Bias Current Modelling Reply

    I have BIAS block and LDO Block.

    BIAS sources 1uA current and LDO sinks the same 1uA current.

     

    BIAS block code:

    Module BIAS_Block(en,supply,bias);

    Input en,supply;

    Inout BIAS;

    Electrical supply,bias;

    Logic en;

    Analog begin

    If(en==1’b1) begin

    I(bias) <+ 1e-6;

    End

    else begin

    I(bias) <+ 0.0;

    End

    Endmodule

     

    LDO block code:

    Module LDO_Block(ldo_en,bias,supply,ldo_out);

    Input ldo_en,supply;

    Inout ldo_out,bias;

    Electrical supply,ldo_out,bias;

    Logic ldo_en;

    Real R_load=5K;

    Analog begin

    V(bias) <+ I(bias)*R_load; //If i do not limit the bias pin voltage,then V(bias) is going to much higher values which is not desirable.

    If(ldo_en==1’b1 && I(bias)>0.8e-6) begin

    V(ldo_out) <+ 1.8;

    End

    else begin

    V(ldo_out) <+ 0.0;

    End

    End

    Endmodule

    Now I want to replace the LDO block with SPICE instead of v-ams.

    In this case does the MOS in LDO block sinking the 1uA bias current limits the voltage of bias pin.


    • Post Points: 20
  • Wed, Sep 4 2013 6:22 AM

    Re: Verilog-AMS Bias Current Modelling Reply

    I see no reason why this should be an issue.

    Regards,

    Andrew.

    • Post Points: 20
  • Wed, Sep 4 2013 6:52 AM

    • shalem7
    • Not Ranked
    • Joined on Thu, Jan 19 2012
    • hyderabad, Andhra Pradesh
    • Posts 9
    • Points 120
    Re: Verilog-AMS Bias Current Modelling Reply

    Thanks Andrew,

    I haven't tried to replace it with SPICE because we are at initial phase of developing the VAMS Models.

    Once i try it and will post my findings for any issues and concerns.

    Thanks,

    Shalem

    • Post Points: 5
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Started by shalem7 at 04 Sep 2013 02:51 AM. Topic has 4 replies.