I'm importing some verilog files into dfII library to
generate a schematic to run a transistor level simulation.The library
for standard cells are created first. When I use verilogin, it can
proceed without errors but there is a weird problem, it will place each
module twice, one with proper connections and one without any
For example, following is a simple verilog file, containing only one inverter.
module test (A, B, VDD, VSS);
INHDV1 inv1 (.VSS ( VSS ), .VDD ( VDD ), .I ( A ), .ZN ( B ) );
is a standard cell and it has ports VDD/VSS/I/ZN. But the imported
schematic has two inverters, where one connects to VDD/VSS/A/B
correctly, and the other has no connections at all.
I tried some options in verilogIn form and read the document. No clues. We are using IC5141usr6.
Could anybody give some suggestions?