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 clocking...endclocking block question in the ifv 

Last post Mon, Aug 26 2013 6:23 AM by DouglasYaya. 2 replies.
Started by DouglasYaya 26 Aug 2013 05:40 AM. Topic has 2 replies and 274 views
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  • Mon, Aug 26 2013 5:40 AM

    clocking...endclocking block question in the ifv Reply
    Hi, All
     
    I am a new beginner in the IFV, now I have a question of  how to implement the clocking...endclocking in IFV.
     
    For the following code, I am intened to see the "din" in the waveform has a delay of 3ns to the "clk", I have never successed, could you tell me wheter the code has some issue(e.g., missed ports declaration) or list several key TCL commands for it?
     
    I really appreciate you help!
     
    Thanks,
    Douglas 

     
     
     
    `timescale 1ns/1ps
    module  reg_s
        (
            clk,
            rst,
            din,
            dout
        );

        input                       rst;
        input                       clk;
        input                       din;

        output                      dout;

        reg                         dout;


        always @(posedge rst or posedge clk)
        begin
            if(rst == 1'b1)
            begin
                dout    <= 1'b0;
            end
            else
            begin
                dout    <= din;
            end
        end
    endmodule


    interface   reg_s_if(input clk);

        logic                       rst;
        logic                       din;
        logic                       dout;

        clocking cb @(posedge clk);
            default input #2ns output #3ns;
            input                 dout;
            output din;
     
    proterty  p_dout;
      ...
    endproperty 
        endclocking
     
        ap_dout :assert  property(p_dout);
     
        modport drv_mp(clocking cb, output rst);

        modport dut_mp(input din, rst, output dout);

    endinterface


    module  tb;

        logic                       clk;
        
        initial
        begin
            clk     = 1'b0;
            forever
            begin
                #5ns;
                clk = ~clk;
            end
        end
        
        reg_s_if        u_reg_s_if(clk);

        reg_s           u_reg_s
                        (
                        .rst    (   u_reg_s_if.rst  ),
                        .clk    (   u_reg_s_if.clk  ),
                        .din    (   u_reg_s_if.din  ),
                        .dout   (   u_reg_s_if.dout )
                        );
                       
    endmodule

    • Post Points: 20
  • Mon, Aug 26 2013 5:58 AM

    • TAM1
    • Top 75 Contributor
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    Re: clocking...endclocking block question in the ifv Reply

     IFV is doing a formal proof and to do so it reduces the circuit description to a cycle-based model. As a cycle-based model, all of the timing information is ignored. The circuit will only change state on the edges of the clocks that you've defined. The effects of a clocking block will only be visible during a simulation run.

    • Post Points: 20
  • Mon, Aug 26 2013 6:23 AM

    Re: clocking...endclocking block question in the ifv Reply

    Thank you, TAM1, you've corrected my understanding!

    Yes, exactly, I can see the timing effect during the simulation run(In QestaSim) but not the IFV.

    BTW, I want to confirm again, you mean the "only simulation run", is that something like such one? Since I successed the timing effect in this pattern.

     program automatic test(...) ;

    logic ...;

    logic ...; 

      dut u_dut(...);

    intial

    begin

    ... 

    end 

    endporgram

     

     

     

    • Post Points: 5
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Started by DouglasYaya at 26 Aug 2013 05:40 AM. Topic has 2 replies.