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 can we attach technology file to verilog-AMS design 

Last post Tue, Aug 27 2013 9:26 PM by Andrew Beckett. 1 replies.
Started by sunilreddy 16 Aug 2013 03:51 AM. Topic has 1 replies and 2449 views
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  • Fri, Aug 16 2013 3:51 AM

    • sunilreddy
    • Not Ranked
    • Joined on Wed, Jun 26 2013
    • Singapore, 00-SG
    • Posts 4
    • Points 65
    can we attach technology file to verilog-AMS design Reply

    Hai all 

    I am new to cadence and verilog-AMS i am trying to design ADC circuit completely in verilog-AMS description.

    i have a doubt that whether we can attach technology file(65nm or 180nm) to this design codes and get the power consumption of the circuit .if any one says yes we can then tell me how to attach the technology file and get the power data

    I am using virtuoso dfII environment (IC6.150

    i am sorry if i have posted in the wrong forum

    thank you in advance for any help 

    • Post Points: 20
  • Tue, Aug 27 2013 9:26 PM

    Re: can we attach technology file to verilog-AMS design Reply

    You could update your models to call the $pwr task (this is a Cadence extension to the Verilog-AMS language) to specify how much power they take. But other than that, unless your models actually model power somehow, attaching a technology (whatever that means in this context) isn't going to help.

    You need some idea of the implementation to be able to compute the power.

    Kind regards,

    Andrew.

    • Post Points: 5
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Started by sunilreddy at 16 Aug 2013 03:51 AM. Topic has 1 replies.