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 Include a IP netlist during Synthesis of a complete design 

Last post Sun, Aug 18 2013 9:53 PM by Bapaiah. 2 replies.
Started by Bapaiah 14 Aug 2013 02:41 AM. Topic has 2 replies and 3741 views
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  • Wed, Aug 14 2013 2:41 AM

    • Bapaiah
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    • Joined on Wed, Aug 14 2013
    • Posts 2
    • Points 25
    Include a IP netlist during Synthesis of a complete design Reply

    I have an IP whose netlist is available. I want to include this netlist during Synthesis of my complete SoC. I do not want to modify anything inside this Netlist. 

     What are the steps to be followed during Synthesis?  

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    • Post Points: 20
  • Fri, Aug 16 2013 7:12 AM

    • bmiller
    • Top 200 Contributor
    • Joined on Tue, Oct 14 2008
    • Ottawa, Ontario
    • Posts 42
    • Points 555
    Re: Include a IP netlist during Synthesis of a complete design Reply

    You would read your HDL and elaborate as follows:

      read_hdl -v2001|-sv <rtl_files>

      read_hdl -netlist <ip_netlsit>

     

    Then, you would preserve the IP block:

      set_attr preserve true [find / -subdesign <ip_module_name>]

     

    Continue with synthesis as you normally would.  The IP module will not be modified, but the paths to and from the IP module will be optimized.

     

    • Post Points: 20
  • Sun, Aug 18 2013 9:53 PM

    • Bapaiah
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    • Joined on Wed, Aug 14 2013
    • Posts 2
    • Points 25
    Re: Include a IP netlist during Synthesis of a complete design Reply
    Thanks a lot for the answer bmiller. 
    • Post Points: 5
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Started by Bapaiah at 14 Aug 2013 02:41 AM. Topic has 2 replies.