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 How to avoid Hidden State in VerilogA model for SpectreRF 

Last post Thu, Jul 4 2013 10:51 AM by RFStuff. 4 replies.
Started by RFStuff 04 Jul 2013 09:35 AM. Topic has 4 replies and 753 views
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  • Thu, Jul 4 2013 9:35 AM

    • RFStuff
    • Top 25 Contributor
    • Joined on Tue, Feb 5 2013
    • Posts 214
    • Points 3,780
    How to avoid Hidden State in VerilogA model for SpectreRF Reply

     Dear All,

    I am a beginner in verilogA .

    I wrote a code but when I ran PSS it showed hidden state in the code and didn't run.

    My behavioural model is as below:-

     

     

    // VerilogA for VERILOG_A_MODEL, HARD_LIMIT_GM, veriloga

    `include "constants.vams"
    `include "disciplines.vams"

    module HARD_LIMIT_GM(in,out);
      inout in,out;
      parameter real vtrans = 0;
      parameter real tdelay = 0 from [0:inf);
      parameter real trise = 1p from (0:inf);
      parameter real tfall = 1p from (0:inf);
      parameter real Gm=-5m;
      electrical in,out;
      real vout_val;
      analog begin
     
             @ (cross(V(in) - vtrans, 1))  vout_val = 1;
             @ (cross(V(in) - vtrans, -1)) vout_val = 0;
     
             I(out) <+ Gm * transition( vout_val, tdelay, trise, tfall); 
      end   
    endmodule

     

    Could anybody please tell how I can avoid the hidden state  (vout_val ) ?

     

    Kind Regards,

    • Post Points: 20
  • Thu, Jul 4 2013 9:57 AM

    Re: How to avoid Hidden State in VerilogA model for SpectreRF Reply

    The reason you have a hidden state is because vout_val is not updated on every iteration. It's only set within the @cross blocks - and is held (and hence retains state) between cross events.

    If you replace the two @cross statements with:

         @ (cross(V(in) - vtrans)) ;
         vout_val = V(in)>vtrans;

    Then it will do what you want. The first @cross will force there to be a timestep close to either the positive or negative transition - but doesn't have any action within the @cross itself. The second line is simply computing the vout_val based on whether V(in) is greater than vtrans - but does this at every timestep and hence is not a hidden state.

    Kind Regards,

    Andrew.

    • Post Points: 20
  • Thu, Jul 4 2013 10:29 AM

    • RFStuff
    • Top 25 Contributor
    • Joined on Tue, Feb 5 2013
    • Posts 214
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    Re: How to avoid Hidden State in VerilogA model for SpectreRF Reply

     Dear Andrew,

    Thanks a lot for your reply. I have some doubts.

    1:- Every iteration means:-

    Is it each simulation time step ?

    2:- Suppose instead of having vout_val= 1 or 0, If I want let's say vout_val= -5 ( for positive edge cross )or +7 ( for -ve edge cross ),

    is there a way to achieve this ?

    Kind Regards,

     

     

    • Post Points: 20
  • Thu, Jul 4 2013 10:36 AM

    Re: How to avoid Hidden State in VerilogA model for SpectreRF Reply
    1. There could be more than one iteration per time step as it converges - but at least it will evaluate the code on every timestep and a state is hidden if it is not assigned a value every time the behavioural code is executed.
    2. Yes - I just simplified it. You could do (instead of my second suggested line):

      if (V(in)>vtrans)
        vout_val=-5;
      else
        vout_val=7;

    Regards,

    Andrew.

    • Post Points: 20
  • Thu, Jul 4 2013 10:51 AM

    • RFStuff
    • Top 25 Contributor
    • Joined on Tue, Feb 5 2013
    • Posts 214
    • Points 3,780
    Re: How to avoid Hidden State in VerilogA model for SpectreRF Reply

     Dear Andrew,

    Thanks a lot for clarifying the Hidden State problem.

    Kind Regards,

     

    • Post Points: 5
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Started by RFStuff at 04 Jul 2013 09:35 AM. Topic has 4 replies.