I am using EDI 10.12.002 to implement a processor design. I have my own library of logic cells which I mix with certain sequential cells, buffers and inverters of a vendor library. The geometric aspects and characterization conditions for the custom library cells match that of vendor librar but there are some differences in that the vendor timing libs are produced using synopsys tools whereas I obtain my libs from ELC.
During the routing phase I get this warning:
#WARNING (NRDR-128) Can not do via swapping using command 'globalDetailRoute', use 'detailRoute' command instead . Will do normal detail routing if possible.
#Using multithreading with 4 threads.
#Worst slack with path group effect 340282346638528859811704183484516925440.000000
What does this indicate?
Additionally, the optimization phase of routing goes on for a really long time and runs for a couple of hours(It has been over two hours now and still going strong). The timing constraint is a very relaxed 30ns and up until the routing phase I get a slack of 18+ ns. I intentionally have a relaxed timing constraint as the custom library cells have small and limited drive strength. I have a few essentaildelay constraints on the input and out put portsof the design but nothing else.
Could the long run times indicate missing false path constraints and/or multi-cycle path constraints? Is there a way to ascertain this and get more information? I suspect that the long runtimes are due to missing/erroneous constraints because I also have a generous floorplan and the design starts out with about 20% density but is buffered up to about 75% density (the slack also falls to only about 0.18ns). What could be the possible reasons for such large discrepancies in the reported slack and is there any way to ensure that false/multi-cycle paths are accurately accounted for?
Any help is appreciated.