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 Group Pin swap 

Last post Fri, Jul 5 2013 7:55 AM by mcatramb91. 6 replies.
Started by package design 26 Jun 2013 10:02 AM. Topic has 6 replies and 1078 views
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  • Wed, Jun 26 2013 10:02 AM

    • package design
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    Group Pin swap Reply
    Hi, I have 4 diff.pairs as one group (1 Quad). I have an option of swapping the pins within the group or I can swap entire group to group. With swap code, I can do the swap within Quad (group). Is it possible to do group swapping (Quad to Quad)? We are using 16.5 and not using FPGA system planner. Regards,Subbu
    • Post Points: 20
  • Wed, Jun 26 2013 4:37 PM

    • redwire
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    Re: Group Pin swap Reply

     You can do this...which tool are you using?

    There is pin swapping and gate swapping in OrCAD - how you draw your symbol will determine which gates are swappable.

    In DE HDL you have to set the pin/gate/function swapping up in the chips.prt file

    • Post Points: 20
  • Thu, Jun 27 2013 1:32 AM

    • package design
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    Re: Group Pin swap Reply
    We are using View Draw for schematics and Allegro16.5 for layout. We ar enot getting an option of gate swapping in View draw. Is it possible to do anything in Cadence PCB Editor, APD or SiP?
    • Post Points: 20
  • Thu, Jun 27 2013 5:19 AM

    • mcatramb91
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    Re: Group Pin swap Reply

    The easiest way is to update your Viewdraw schematic symbol so it generates the correct Device file for gate/pin swapping to occur.

    Attached is a simple example of a Resistor Pack device file generated from Viewdraw which allows gate/pin swapping by using a HETERO Type 4 schematic symbol in Viewdraw.   I presented a paper at CDNLive some time ago that talks about the migration from DxDesigner (Viewdraw) Library to Allegro Design Entry HDL Library which is available on the Cadence web site.

    Here is a link => http://www.cadence.com/rl/Resources/conference_papers/7.13Presentation.pdf

    On Pages 34 thru 38 it explains HETERO Type 4 and how it is used in Viewdraw to allow gate swapping on the Allegro side by generating the Device file and Netlist with functional gates so swapping can occur, also you will have the ability to back-annotation the swaps as well.

    Hope this helps,
    Mike Catrambone


    • Post Points: 35
  • Mon, Jul 1 2013 7:43 PM

    • package design
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    Re: Group Pin swap Reply
    Hi, Thanks for all your responses. We are getting the following errors while we do make PCB (generating netlist). How to resolve this?


    Total errors - 0 and warnings - 0

    pcb: Error 6092: zircon com SAPIR0: Bad hetero device SAPIR-1, symbol CURRENT_PROJECT:SAPIR_1
    pcb: Error 6092: zircon com SAPIR0: Bad hetero device SAPIR-1, symbol CURRENT_PROJECT:SAPIR_2
    pcb: Error 6092: zircon com SAPIR0: Bad hetero device SAPIR-1, symbol CURRENT_PROJECT:SAPIR_3
    pcb: Error 6092: zircon com SAPIR0: Bad hetero device SAPIR-1, symbol CURRENT_PROJECT:SAPIR_4
    pcb: Error 6092: zircon com SAPIR0: Bad hetero device SAPIR-1, symbol CURRENT_PROJECT:SAPIR_5
    pcb: Error 6092: zircon com SAPIR0: Bad hetero device SAPIR-1, symbol CURRENT_PROJECT:SAPIR_6
    pcb: Error 6092: zircon com SAPIR0: Bad hetero device SAPIR-1, symbol CURRENT_PROJECT:SAPIR_7
    pcb: Error 6092: zircon com SAPIR0: Bad hetero device SAPIR-1, symbol CURRENT_PROJECT:SAPIR_8
    pcb: Error 6092: zircon com SAPIR0: Bad hetero device SAPIR-1, symbol CURRENT_PROJECT:SAPIR_9
    pcb: Error 6092: zircon com SAPIR1: Bad hetero device SAPIR-1, symbol ASICS:SAPIR-1_1H
    pcb: Error 6092: zircon com SAPIR1: Bad hetero device SAPIR-1, symbol ASICS:SAPIR-1_2H
    pcb: Error 6092: zircon com SAPIR1: Bad hetero device SAPIR-1, symbol ASICS:SAPIR-1_3H
    pcb: Error 6092: zircon com SAPIR1: Bad hetero device SAPIR-1, symbol ASICS:SAPIR-1_4H
    pcb: Error 6092: zircon com SAPIR1: Bad hetero device SAPIR-1, symbol ASICS:SAPIR-1_5H
    pcb: Error 6092: zircon com SAPIR1: Bad hetero device SAPIR-1, symbol ASICS:SAPIR-1_6H
    pcb: Error 6092: zircon com SAPIR1: Bad hetero device SAPIR-1, symbol ASICS:SAPIR-1_7H
    pcb: Error 6092: zircon com SAPIR1: Bad hetero device SAPIR-1, symbol ASICS:SAPIR-1_8H
    pcb: Error 6092: zircon com SAPIR1: Bad hetero device SAPIR-1, symbol ASICS:SAPIR-1_9H
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_1: PINSWAP=([R43],[N40]): Bad pin name: R43
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_1: PINSWAP=([R43],[N40]): Bad pin name: N40
    pcb: Error 7108: zircon sym CURRENT_PROJECT:SAPIR_1: PINSWAP=([R43],[N40]): Pinswap attribute requires at least 2 pins.
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_2: PINSWAP=([R43],[N40]): Bad pin name: R43
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_2: PINSWAP=([R43],[N40]): Bad pin name: N40
    pcb: Error 7108: zircon sym CURRENT_PROJECT:SAPIR_2: PINSWAP=([R43],[N40]): Pinswap attribute requires at least 2 pins.
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_3: PINSWAP=([R43],[N40]): Bad pin name: R43
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_3: PINSWAP=([R43],[N40]): Bad pin name: N40
    pcb: Error 7108: zircon sym CURRENT_PROJECT:SAPIR_3: PINSWAP=([R43],[N40]): Pinswap attribute requires at least 2 pins.
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_4: PINSWAP=([R43],[N40]): Bad pin name: R43
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_4: PINSWAP=([R43],[N40]): Bad pin name: N40
    pcb: Error 7108: zircon sym CURRENT_PROJECT:SAPIR_4: PINSWAP=([R43],[N40]): Pinswap attribute requires at least 2 pins.
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_5: PINSWAP=([R43],[N40]): Bad pin name: R43
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_5: PINSWAP=([R43],[N40]): Bad pin name: N40
    pcb: Error 7108: zircon sym CURRENT_PROJECT:SAPIR_5: PINSWAP=([R43],[N40]): Pinswap attribute requires at least 2 pins.
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_6: PINSWAP=([R43],[N40]): Bad pin name: R43
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_6: PINSWAP=([R43],[N40]): Bad pin name: N40
    pcb: Error 7108: zircon sym CURRENT_PROJECT:SAPIR_6: PINSWAP=([R43],[N40]): Pinswap attribute requires at least 2 pins.
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_7: PINSWAP=([R43],[N40]): Bad pin name: R43
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_7: PINSWAP=([R43],[N40]): Bad pin name: N40
    pcb: Error 7108: zircon sym CURRENT_PROJECT:SAPIR_7: PINSWAP=([R43],[N40]): Pinswap attribute requires at least 2 pins.
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_8: PINSWAP=([R43],[N40]): Bad pin name: R43
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_8: PINSWAP=([R43],[N40]): Bad pin name: N40
    pcb: Error 7108: zircon sym CURRENT_PROJECT:SAPIR_8: PINSWAP=([R43],[N40]): Pinswap attribute requires at least 2 pins.
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_9: PINSWAP=([R43],[N40]): Bad pin name: R43
    pcb: Error 6120: zircon sym CURRENT_PROJECT:SAPIR_9: PINSWAP=([R43],[N40]): Bad pin name: N40
    pcb: Error 7108: zircon sym CURRENT_PROJECT:SAPIR_9: PINSWAP=([R43],[N40]): Pinswap attribute requires at least 2 pins.
    pcb: Error 6079: zircon sym ASICS:SAPIR-1_1H: PKG_TYPE=FBGA-2112-S0-PB_R: Hetero device attribute conflict
    pcb: Error 6079: zircon sym ASICS:SAPIR-1_1H: HETERO=(SAPIR-1_1H),(SAPIR-1_2H),(SAPIR-1_3H),(SAPIR-1_4H),(SAPIR-1_5H),(SAPIR-1_6H),(SAPIR-1_7H),(SAPIR-1_8H),(SAPIR-1_9H): Hetero device attribute conflict
    pcb: Error 6079: zircon sym ASICS:SAPIR-1_1H: DEVICE=SAPIR-1: Hetero device attribute conflict
    pcb: Note 6085: zircon pkg RN28: 1 empty slot(s), device RNWISO1KTF4R63MW5PCRA8
    pcb: Note 6085: zircon pkg RN27: 1 empty slot(s), device RNWISO1KTF4R63MW5PCRA8
    pcb: Note 5626: Summary of vl2al.err
    Status 1, Notes 4374, Warnings 2335
    Errors 48, Failures 0, Fatals 0, Internals 0
    PCB Forward Interface - V6.1; DxDesigner 2005.0 (030305)

    • Post Points: 5
  • Thu, Jul 4 2013 10:03 AM

    • package design
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    Re: Group Pin swap Reply
    Hi,

    How to assign function G1 G2 G3….in device file through viewdraw symbols or schematics? When we generate the netlist, we are getting a default function G1 along with all signal pin number. I could edit the device file manually, but it will not sync with Schematics. Pls suggest.

    Regards,

    Subbu
    • Post Points: 20
  • Fri, Jul 5 2013 7:55 AM

    • mcatramb91
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    Re: Group Pin swap Reply

    Basically, you will need to create separate schematic symbol with represents the gate of the device which is referenced by the complete block schematic symbol via the HETRO property.  Please review the presentation via the link on my previous post, it should answer your questions.

     

    • Post Points: 5
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Started by package design at 26 Jun 2013 10:02 AM. Topic has 6 replies.