I have mixed language in my design (Verilog and VHDL).
I notice that AFA is generated only for Verilog and not VHDL. Is this a problem with the tool?
IFV support AFA in all HDL languages including VHDL, Verilog and SystemVerilog. What you experience is either a setup or a tool problem.
Thank you for your immediate reply.
I have used the irun command, any irun option that I could have used that could have prevented AFA for VHDL?