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 Asynchronous FIFO design 

Last post Sun, Oct 27 2013 9:31 AM by KennyWylies. 7 replies.
Started by abhinavpr 18 Jun 2013 03:56 AM. Topic has 7 replies and 10005 views
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  • Tue, Jun 18 2013 3:56 AM

    • abhinavpr
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    Asynchronous FIFO design Reply

     Hi,

             I am new to logic design and trying to design an Asynchronous FIFO. can somebody suggest some good docs to read?

     

    regards,

    abhinavpr

    • Post Points: 50
  • Tue, Jun 18 2013 5:47 AM

    • grasshopper
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    Re: Asynchronous FIFO design Reply

    Here goes a suggestion

     

    Principles of Asynchronous Circuit Design: A Systems Perspective (European Low-Power Initiative for Electronic System Design) [Paperback]
    Jens Sparsø , Steve Furber
     
    gh-

     

    • Post Points: 20
  • Wed, Jun 19 2013 5:34 AM

    • abhinavpr
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    Re: Asynchronous FIFO design Reply
    Thanks for the response. The book is goond for understanding the aspects of asynchronous design but the FIFO presented in the book is somewhat peculiar and uses shift register and not a generic fifo. However i came across a paper by cliff cummings on FIFO design which was very basic and well explained.

    As it seems that paper is quite famous  i would like to ask some question regarding the design in the paper or Async FIFO design in general as the design is very basic

    1) In the design 2 FF synchronizer is used for both read pointer and write pointer . won't it depend on clock domain crossing?as from slow to fast CDC using a 2 FF synchronizer is fine but from fast to slow CDC the 2 FF design may not work. so should we be using different synchronizer at fast to slow CDC and slow to fast CDC.

    2)  Full and empty check :  He has written that the updation would be immediate but i think differently,
        assuming a situation where W_clk is faster than R_clk, two cases would arrive
         a) when w_clk is marginally faster than the R_clk then the Rpointer value in the write pointer domain would arrive 2 rclk cycles later
              and hence FIFO FULL would be asserted at FIFO depth -2.
        
         b) when W_clk is much faster than the R_clk then the Rpointer value in the write pointer domain would arrive 2 rclk cycles later
              and hence FIFO FULL would be asserted at FIFO depth - (some value).
            in both the case the FIFO FULL detection is not immediate. and same goes for empty check condition too (applying different set of conditions).

     plz enlighten me on the issue.

    regards,

    abhinavpr
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    • Post Points: 20
  • Wed, Jun 19 2013 12:44 PM

    • glennramalho
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    Re: Asynchronous FIFO design Reply

    Also if you are interested, there is a famous paper on asynchronous FIFOs.

     

    http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf

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  • Wed, Jun 19 2013 9:34 PM

    • abhinavpr
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    Re: Asynchronous FIFO design Reply

     I have gone through that paper too but even there it is not explained.

    Plz somebody help me.

     

    • Post Points: 20
  • Sat, Jul 20 2013 11:35 AM

    • Paul Bibin
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    Re: Asynchronous FIFO design Reply

     FIFO is nothing but a set of registers.Normally used in highthroughput requirement systems.Data read /write when FIFO empty /full creates issues ,so we need to design additional control logic for the same.My suggestion is to understand syncronous FIFO first ,then undestand the problem of metastability and CDC reconvergence ,followed by grey code solution.Plenty of materials are available in the internet.

    • Post Points: 5
  • Sun, Sep 15 2013 4:43 AM

    Re: Asynchronous FIFO design Reply

    Im also having a task of desigining Asyn. FIFO.. i have gone through that paper. please explain me about the gray pointer comparision.

    Thanks. 

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  • Sun, Oct 27 2013 9:31 AM

    • KennyWylies
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    Re: Asynchronous FIFO design Reply
    Hi, You should view video tutorial about that topice you should found excellent tutorial on it.
    • Post Points: 5
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Started by abhinavpr at 18 Jun 2013 03:56 AM. Topic has 7 replies.