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 model card vith a verilogA model through spectre 

Last post Mon, Mar 17 2014 3:13 AM by Fabb. 11 replies.
Started by Fabb 17 Jun 2013 01:42 AM. Topic has 11 replies and 1557 views
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  • Mon, Jun 17 2013 1:42 AM

    • Fabb
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    • Joined on Mon, Jun 17 2013
    • Grenoble, Isere
    • Posts 22
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    model card vith a verilogA model through spectre Reply

    Hello,

    I would like to run my own verilogA model with spetcre through a model card approach.

    Nevertheless my model paramaters are not recognized, so not took into account in the simulation

    #------------------------mymodel.va
    module mymodel(T1,T2);
        
        inout T1, T2;
        electrical T1, T2;

        // instance parameters
        parameter real    ip1=1;
        //Technology Parameters
        parameter real tp1=1;
            analog begin
            @(initial_step)
            begin
                $strobe("----> mymodel");
                $display("Instance parameters: ip1=%r, ip1);
                $display("Technology parameters: tp1=%r , tp1);
            end
        endmodule

    #------------------------model card
    simulator lang=spectre

    library test

    section means
        parameters efftp1 = 777
            include "model_cards.scs" section=core
    endsection means


    section core
        ahdl_include "mymodel.va"        
        model device1 mymodel
            +tp1 = efftp1
    endsection core
    endlibrary

    #------------------------cdf parameters
    ((nil name "ip1" paramType "string" defValue "1" prompt "ip1" choices nil parseAsNumber t units "lengthMetric" use nil display nil editable nil dontSave nil callback nil storeDefault t parseAsCEL t) (nil name "model" paramType "string" defValue "" prompt "model name" choices nil parseAsNumber nil units nil use nil display nil editable nil dontSave nil callback nil storeDefault nil parseAsCEL t))
    (nil spectre (nil modelParamExprList "" optParamExprList "" opParamExprList "" stringParameters "" propMapping "" termMapping "nil T1 \\:1 T2 \\:2" termOrder "T1 T2" componentName "" instParameters "radius" otherParameters "model" netlistProcedure "") hspiceD (nil opParamExprList "" optParamExprList "" propMapping "" termMapping "" termOrder "" namePrefix "" componentName "" instParameters "" otherParameters "" netlistProcedure "") auLvs (nil namePrefix "" permuteRule "" propMapping "" deviceTerminals "" termOrder "" componentName "" instParameters "" otherParameters "" netlistProcedure "") auCdl (nil dollarEqualParams "" dollarParams "" modelName "" namePrefix "" propMapping "" termOrder "" componentName "" instParameters "" otherParameters "" netlistProcedure "") ams (nil isPrimitive "" extraTerminals "" propMapping "" termMapping "" termOrder "" componentName "" excludeParameters "" arrayParameters "" stringParameters "" referenceParameters "" enumParameters "" instParameters "" otherParameters "" netlistProcedure ""))
    (nil paramLabelSet nil opPointLabelSet nil modelLabelSet nil paramDisplayMode nil paramEvaluate "nil nil nil nil nil" paramSimType nil termDisplayMode nil termSimType nil netNameType nil instDisplayMode nil instNameType nil)
    (nil doneProc "" formInitProc "" promptWidth 175 fieldWidth 350 buttonFieldWidth 340 fieldHeight 35)

    #------------------------error message

    tp1 not recognized in mymodel.va


    How should I proceed to allow parameters to be modified in a modelCard.

    Regards,

    Fabrice

    • Post Points: 20
  • Mon, Jun 24 2013 3:03 PM

    Re: model card vith a verilogA model through spectre Reply

    Fabrice,

    Other than the syntax errors in your VerilogA module (missing quotation marks, missing  end statement, you also need some attributes to tell it that it is a "compact module" and which parameters are instance (versus model) parameters. So changing it to this:

     `include "disciplines.vams"

    (* compact_module *)
    (* instance_parameter_list ={ip1} *)
    module mymodel(T1,T2);
        
        inout T1, T2;
        electrical T1, T2;

        // instance parameters
        parameter real    ip1=1;
        //Technology Parameters
        parameter real tp1=1;
          analog begin
            @(initial_step)
            begin
                $strobe("----> mymodel");
                $display("Instance parameters: ip1=%r", ip1);
                $display("Technology parameters: tp1=%r" , tp1);
            end
          end
    endmodule

    Does what you want. Note that there's a typo in the documentation with regards to the instance_parameter_list attribute - it doesn't show the "=" in the documentation. CCR 808807 is to get this fixed.

    Regards,

    Andrew.

    • Post Points: 20
  • Tue, Jun 25 2013 4:56 AM

    • Fabb
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    • Joined on Mon, Jun 17 2013
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    Re: model card vith a verilogA model through spectre Reply
     Andrew,

     

    Thanks a lot, indeed your solution is helping me.

    The two statements

    (* compact_module *)
    (* instance_parameter_list ={ip1} *)

    are probably  mandatories only for spectre, isn't it?

    Secondly, these two statments are not documented neither in varilogA doc or spectre doc, is it normal?

     

    Regards,


    Fabrice

     

    • Post Points: 20
  • Tue, Jun 25 2013 6:00 AM

    Re: model card vith a verilogA model through spectre Reply

    Fabrice,

    They are documented in the VerilogA manual (in MMSIM11.1 and MMSIM12.1 at least; I didn't check older releases). I don't know if they are supported in other simulators. Other simulators would also need to know the difference between instance and model parameters, if they support compact device modelling in VerilogA.

    Kind Regards,

    Andrew.

    • Post Points: 50
  • Tue, Jun 25 2013 6:24 AM

    • Fabb
    • Top 500 Contributor
    • Joined on Mon, Jun 17 2013
    • Grenoble, Isere
    • Posts 22
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    Re: model card vith a verilogA model through spectre Reply

     indeed i was looking for in an old doc.

     

    thanks again for your help

     

    fab

    • Post Points: 5
  • Wed, Jul 24 2013 7:26 AM

    • kjabeur
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    • Joined on Tue, Jul 23 2013
    • Posts 2
    • Points 25
    Re: model card vith a verilogA model through spectre Reply

    Hello,

     In my case I am declaring new quantities (nature and discipline) in my veriloga file.

    I needed this to boost the value of the blowup in order to avoid some convergence problems I encountered.

    Now, I target to set my model card.

    using the lines : `include "disciplines.vams"   //(* compact_module *)  (* instance_parameter_list ={a,b} *)  on top of my code, I get tghe following error when I launch my simulations  ""Error found by spectre during AHDL read-in.  ERROR (VACOMP-2259): "nature<<--?  new_current"

    Although when I don't use  //(* compact_module *)  (* instance_parameter_list ={a,b} *)  on top of my code and subsequently I use subckt in my .scs file I don't have any error and that works good !

    To conclude, can We deduce that I can not use new quantities in my veriloga code if I use  //(* compact_module *)  (* instance_parameter_list ={a,b} *)  on top of my code ?

    Thanks in advance

     Best regards 

    Kotb 

    • Post Points: 5
  • Sun, Mar 16 2014 1:27 AM

    Re: model card vith a verilogA model through spectre Reply

    Hello,

    I am defining BSIMCMG verilog-a model in cadence and I created a symbol for it, but I dont know how to attache the model card with this model. As when I run simulation, since the model card is not defined, these missing model parameters  appear as undefined design variables that need to be defined manually.

    I would like to know how to define the model card to define these parameters automatically 
    The model card is in spice format:

    .model nmos1 bsimcmg
    + BULKMOD = 1
    + CAPMOD = 0
    + COREMOD = 0
    ...

    Thanks

    • Post Points: 20
  • Sun, Mar 16 2014 1:50 AM

    Re: model card vith a verilogA model through spectre Reply

    First of all, bsimcmg is available as a built-in model in spectre, so using a VerilogA model is going to be less efficient.

    You can specify the model card via Setup->Model Libraries in ADE. It's fine if it's in SPICE syntax - just make sure that the file does not have the ".scs" suffix (any other suffix will be assumed to be in SPICE syntax).

    If you really do need to use the VerilogA model, you'd have to ensure that the VerilogA module has the correct attributes to ensure that the parameters are recognized as model parameters - but maybe you won't need to do that...

    Regards,

    Andrew.

    • Post Points: 20
  • Sun, Mar 16 2014 2:10 AM

    Re: model card vith a verilogA model through spectre Reply

    Yea, I know that bsimcmg is built-in in spectre, but i need to define the verilog-a.

    I defined it before in the model librareis, but still can't be read by the verilog-a, I think that I miss these correct attributes, are there some lines I need to add to the verilog-a file to recognize that model card defined in the model library?

    Thanks,

     

    • Post Points: 20
  • Sun, Mar 16 2014 3:19 AM

    Re: model card vith a verilogA model through spectre Reply

    I was searching for where I'd answered this (the attributes needed) before, and realised that you've appended to the same thread where I'd answered it already!

    With the attributes in the post, it tells spectre which parameters are instance parameters (and the rest are model parameters) - and having done that you can then specify a model card. You would have to include the veriloga model via a model file too (you can't really have it as a view, because you want the module to be generic and not just for that view). So you'd have your transistor symbol with the CDF set up with all the instance parameters you want to be able to pass to the model, and the spectre simulation information set up to netlist those parameters, and with the model parameter set to "nmos1" or whatever you've called it. You'd have a spectre view (copy of the symbol) to tell it to stop at that point. You could (say) copy from nmos4 in analogLib and then change the CDF parameters to suit your needs (Tools->CDF->Edit and set the CDF type to "Base").

    Then you'd have a file which you'd add to your model files - say "myBsimcmg.scs" which contains:

    ahdl_include "/path/to/bsimcmg.va"

    As well as referencing your model file.

    Regards,

    Andrew.

    • Post Points: 20
  • Sun, Mar 16 2014 7:39 AM

    Re: model card vith a verilogA model through spectre Reply
    1- In case of using the verilog-a model:
    -- In the model card it is specified in the first line:
       .model nmos1 bsimcmg 
       Will the word ''bsimcmg'' refer to the verilog-a file or the built-in bsimcmg in spectre.
       (how it will differentiate between the verilog-a and the built-in model, I created the symbol from the verilog-a to excute the verlog-a           model and I thought that we should use the symbol nmos4 for the built-in bsimcmg )
    -- Regarding the attributes for the verilog-a, Do I need to add only these 2 lines:
     (* compact_module *)
     (* instance_parameter_list ={ip1} *)
     
    2- If I would like to use the built-in bsimcmg in spectre, what I did is:
    - I defined the modelcard in the model libraries 
    - I used the nmos4 in analogLib 
    - I specified the model name: nmos1 (as inicated in the modelcard)
    - Then I used CDF->Edit  and set the CDF type to base to add coressponding parameters like nfin,hfin,tfin,....
    When I run simulation I get the characteristics but the added parameters have no effect on the operation (not defined properly)
    So How can I define them properly?
     
    Sorry for the long post, and thanks very much for your help. 
    • Post Points: 20
  • Mon, Mar 17 2014 3:13 AM

    • Fabb
    • Top 500 Contributor
    • Joined on Mon, Jun 17 2013
    • Grenoble, Isere
    • Posts 22
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    Re: model card vith a verilogA model through spectre Reply

    Amhed,

    This is the template I use in my model card

    section MODELS_CORE
       
        inline subckt myDevice (pin1 pin2 pin3 ....) // myDevice should be identical to symbol name
                 // CDF parameters
                 parameters p1 p2 p3 ...
               
                myDevice (pin1 pin2 pin3 .... ) my_device
                 // instance parameters
            + p1=p1 p2=p2 p3=p3

            model my_device myModelName // myModelName name of your verilogA module
                // techno parameters
                + tp1 = 1.111
                + tp2 = 2.222
                  ......
        ends myModelName          
    endsection MODELS_CORE

    And you need to add 

    (* compact_module *)
    (* instance_parameter_list ={p1,p2,p3 ....} *)

    in your verilogA file

    Regards,

    Fabrice

     

     

    • Post Points: 5
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Started by Fabb at 17 Jun 2013 01:42 AM. Topic has 11 replies.