Thank you for your help.
gh, when I do multiple mapping, the synthesis result is different I don't know why. sometimes, the area geos form 630 to 570. and sometime if you make more mapping the area goes up again. !!
I used to run DC before I switch to RC. DC has a better performance in terms of Area optimization. I guess one of the main reason of that, DC accepts the PLA format (tabular format) which allow me to put some Don't care sets of my design. This gives DC a relaxation space to get more optimized design in terms of Area, power, and Delay.
Also, Do i need to put any delay constraints for my computational circuits in my script shown above to get better area performance??
By the way, I added these constraints to the above script:
set_attribute dp_area_mode true /
set incremental_opto 0
in addition to these, I don't know if they are valid or not :) They are just a guess. :)
set global_area 1
set max_area 0
set area_down 1
Thanks a lot.