Home > Community > Forums > Functional Verification > which all signals need to be initialized in a module

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 which all signals need to be initialized in a module 

Last post Mon, Jun 17 2013 10:28 PM by BharathECE. 2 replies.
Started by BharathECE 13 Jun 2013 02:22 AM. Topic has 2 replies and 516 views
Page 1 of 1 (3 items)
Sort Posts:
  • Thu, Jun 13 2013 2:22 AM

    • BharathECE
    • Not Ranked
    • Joined on Fri, Mar 22 2013
    • Hyderabad, Andhra Pradesh
    • Posts 12
    • Points 210
    which all signals need to be initialized in a module Reply

    Hi

     Iam doing formal verification,Iam getting so many signals unitialized.Iam not understanding which signals we should initialize.How to know which signals we should initialize in a module.

    Filed under: ,
    • Post Points: 20
  • Mon, Jun 17 2013 4:04 PM

    Re: which all signals need to be initialized in a module Reply

    BharathECE,

    This is not a formal only question.  What does the designer or spec say about resetting the design?  If you are running simulation you have the same concerns.

    To initialize the design in IEV, use the tcl force commands to drive the reset signals to their appropriate values and then use the run command to run the clocks.

    clock -add clk 

    force reset_n 0
    # Run the reset for 5 clocks
    run 10
    # Load formal model with initialization state
    init -load -current
    # Display flop values
    init -show

    Hope this helps jumpstart you.

    • Post Points: 20
  • Mon, Jun 17 2013 10:28 PM

    • BharathECE
    • Not Ranked
    • Joined on Fri, Mar 22 2013
    • Hyderabad, Andhra Pradesh
    • Posts 12
    • Points 210
    Re: which all signals need to be initialized in a module Reply

    Hi

     Thanks for the reply,

     

    Its true this question was nothing related to IFV.Actually in any design we need to have some signals initialized as per design after reset process completed.

    That we can do by doing signal force. These things need to be discussed with designer of particular block/module.

     

    Thanks

    Bharath 

     

    Filed under: , ,
    • Post Points: 5
Page 1 of 1 (3 items)
Sort Posts:
Started by BharathECE at 13 Jun 2013 02:22 AM. Topic has 2 replies.