This is not a formal only question. What does the designer or spec say about resetting the design? If you are running simulation you have the same concerns.
To initialize the design in IEV, use the tcl force commands to drive the reset signals to their appropriate values and then use the run command to run the clocks.
clock -add clk
force reset_n 0
# Run the reset for 5 clocks
# Load formal model with initialization state
init -load -current
# Display flop values
Hope this helps jumpstart you.