Home > Community > Forums > Mixed-Signal Design > NC-Verilog Integration netlister explicitly option

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 NC-Verilog Integration netlister explicitly option 

Last post Thu, Jun 13 2013 6:56 PM by Provence. 3 replies.
Started by Provence 05 Jun 2013 06:19 PM. Topic has 3 replies and 1117 views
Page 1 of 1 (4 items)
Sort Posts:
  • Wed, Jun 5 2013 6:09 PM

    • Provence
    • Not Ranked
    • Joined on Mon, Aug 16 2010
    • Shanghai, Shanghai
    • Posts 8
    • Points 130
    Virtuoso Verilog Environment for NC-Verilog integration Reply
    Hi all,

    Through Virtuoso Verilog Environment for NC-Verilog Integration ,I initialize a analog design ,then setup netlist explicitly option to ture.

    I hope to generate  that the netlister used the pin name method as following .

    The result is out of my expectation. some part of netlist remain the pin order method. below is example.

     PIN ORDER:

    transmitter_driver_TX I2 ( .tx_control(net0159), .en_lpcd(en_LP), .U6(net044), .U5(net045), .U4(net046), .U3(net047),      .U2(net048), .U1(net049), .D4(net050), .D3(net051), .D2(net0130), .D1(net052), .TX(TX2));

     
    PIN NAME :

     transmitter_top I10 ( pad_Tx1, pad_Tx2, AS_sel, CWGsPReg[0], CWGsPReg[1], CWGsPReg[2], CWGsPReg[3], CWGsPReg[4],

         CWGsPReg[5], data, force100ask, GsNReg[0], GsNReg[1], GsNReg[2], GsNReg[3], GsNReg[4], GsNReg[5], GsNReg[6], GsNReg[7],

         ModGsPReg[0], ModGsPReg[1], ModGsPReg[2], ModGsPReg[3], ModGsPReg[4], ModGsPReg[5], Tx1rfen, Tx2cw, Tx2rfen,

         en_trans_lp, enb_transmitt, invTx1rf, invTx2rf, net272);

     

    Now, Can anyone tell why ? What happen , transmitter_top I10 ?
    • Post Points: 5
  • Wed, Jun 5 2013 6:19 PM

    • Provence
    • Not Ranked
    • Joined on Mon, Aug 16 2010
    • Shanghai, Shanghai
    • Posts 8
    • Points 130
    NC-Verilog Integration netlister explicitly option Reply
    Hi all,

    Through Virtuoso Verilog Environment for NC-Verilog Integration ,I initialize a analog design ,then setup netlist explicitly option to ture.

    I hope to generate  that the netlister used the pin name method as following .

    The result is out of my expectation. some part of netlist remain the pin order method. below is example.

     PIN ORDER:

    transmitter_driver_TX I2 ( .tx_control(net0159), .en_lpcd(en_LP), .U6(net044), .U5(net045), .U4(net046), .U3(net047),      .U2(net048), .U1(net049), .D4(net050), .D3(net051), .D2(net0130), .D1(net052), .TX(TX2));

     

    PIN NAME :

     transmitter_top I10 ( pad_Tx1, pad_Tx2, AS_sel, CWGsPReg[0], CWGsPReg[1], CWGsPReg[2], CWGsPReg[3], CWGsPReg[4],

         CWGsPReg[5], data, force100ask, GsNReg[0], GsNReg[1], GsNReg[2], GsNReg[3], GsNReg[4], GsNReg[5], GsNReg[6], GsNReg[7],

         ModGsPReg[0], ModGsPReg[1], ModGsPReg[2], ModGsPReg[3], ModGsPReg[4], ModGsPReg[5], Tx1rfen, Tx2cw, Tx2rfen,

         en_trans_lp, enb_transmitt, invTx1rf, invTx2rf, net272);

     

    Now, Can anyone tell why ? What happen , transmitter_top I10 ?

    • Post Points: 20
  • Mon, Jun 10 2013 7:00 AM

    Re: NC-Verilog Integration netlister explicitly option Reply

    For some reason your post was locked (I assume you locked it...) - luckily as moderator I can unlock it, but locking a post means that nobody can reply!

    The NC Verilog netlister will report in the CIW any time it can't meet explicit netlisting, and why. Usually it's because of split busses, which may be the case here - sometimes the syntax doesn't really allow passing by name if you have split busses. But the CIW log should tell you the reason - did you look at that?

    Kind Regards,

    Andrew.

    • Post Points: 35
  • Thu, Jun 13 2013 6:56 PM

    • Provence
    • Not Ranked
    • Joined on Mon, Aug 16 2010
    • Shanghai, Shanghai
    • Posts 8
    • Points 130
    Re: NC-Verilog Integration netlister explicitly option Reply

     as  you say , I find some warning messages that specify CEll has split buses across module ports and module will printted out with ranges.

    Thanks for your help.

    • Post Points: 5
Page 1 of 1 (4 items)
Sort Posts:
Started by Provence at 05 Jun 2013 06:19 PM. Topic has 3 replies.