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 How to preserve the internal signal name in synthesis when using Cadence RTL compiler 

Last post Wed, Jun 5 2013 11:48 AM by rexnyu. 0 replies.
Started by rexnyu 05 Jun 2013 11:48 AM. Topic has 0 replies and 520 views
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  • Wed, Jun 5 2013 11:48 AM

    • rexnyu
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    • Joined on Tue, Mar 26 2013
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    How to preserve the internal signal name in synthesis when using Cadence RTL compiler Reply

    Here is part of my script.

    set_attribute write_vlog_preserve_net_name true
    
    elaborate aes_fwd_top
    
    ungroup -flatten -all
    
    synthesize -to_mapped
    
    write_hdl -mapped > aes_fwd_top-orig.v
    

    But RTL compiler keeps changing my internal signal names with some random names in the verilog netlist file.

    What is the proper way to use "write_vlog_preserve_net_name"? or I am using the wrong command.

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    • Post Points: 5
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Started by rexnyu at 05 Jun 2013 11:48 AM. Topic has 0 replies.