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 Getting vhdl constants in system verilog 

Last post Mon, Jun 3 2013 8:26 AM by rajay. 2 replies.
Started by rajay 03 Jun 2013 05:00 AM. Topic has 2 replies and 505 views
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  • Mon, Jun 3 2013 5:00 AM

    • rajay
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    • Joined on Mon, Jun 3 2013
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    • Points 30
    Getting vhdl constants in system verilog Reply

    Hi,

     I need to re-use the constants and record type variables  in system verilog which are defined in vhdl DUT (in a separate package file). I could not find the idle way to do this task except rewriting the constants in systemverilog again with some manual work. I tried with import statement but didnt work. I was not sure whether i need to add any extra command line arguments to do this. Could any one please shed a light on this?

     

    Thanks for your time.

     

    Regards,

    raja 

    • Post Points: 20
  • Mon, Jun 3 2013 6:54 AM

    • StephenH
    • Top 25 Contributor
    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
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    Re: Getting vhdl constants in system verilog Reply

    Hi Raja.

    This isn't something which is supported in the current simulator version. We do however have a tool to make type conversions.

    If you PM me with your company email address, I can help you.

    Regards,
    Steve.

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
    • Post Points: 20
  • Mon, Jun 3 2013 8:26 AM

    • rajay
    • Not Ranked
    • Joined on Mon, Jun 3 2013
    • Posts 3
    • Points 30
    Re: Getting vhdl constants in system verilog Reply

    Thanks Steve for the update. You can send me details to dasakumar.yenigalla@soctronics.com.

    Thanks,

    Raja 

    • Post Points: 5
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Started by rajay at 03 Jun 2013 05:00 AM. Topic has 2 replies.