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 Gate Level Sim - SDF annotation debug 

Last post Wed, May 29 2013 5:51 AM by andymont. 1 replies.
Started by andymont 23 May 2013 04:22 AM. Topic has 1 replies and 801 views
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  • Thu, May 23 2013 4:22 AM

    • andymont
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    • Joined on Tue, Sep 4 2012
    • Posts 4
    • Points 50
    Gate Level Sim - SDF annotation debug Reply

    Hi, 

    I am trying to annotate an SDF to my gate level synthesis netlist and I am seeing some strange behaviour.

    When I annotate using just the netlist, cell_lib and sdf , everything works fine. However, when I try to annotate using the testbench and providing the full scope to the netlist within the verification environment (SCOPE=test_env.<scopetodigtop>.udig_top), I see thousands of 

    SDFNEP, SDFNET errors. The paths and timing checks which ncelab is complaining about definitely do exist in the cell_lib verilog, and the scope is definitely correct. I have tried modifying the scope just to make sure that it was correct and with anything apart from these settings the annotator complains that the scope is incorrect and refuses to proceed.

    What am I missing and what is the best way to debug this ?

    I have tried versions incisiv/11.10.011, incisiv/12.10.011 and incisiv/12.20.008 

    thanks

    Andy 

    • Post Points: 5
  • Wed, May 29 2013 5:51 AM

    • andymont
    • Not Ranked
    • Joined on Tue, Sep 4 2012
    • Posts 4
    • Points 50
    Re: Gate Level Sim - SDF annotation debug Reply
    Found the issue. My run script had inherited a '-delay_mode unit' switch which for some reason meant that Incisiv knew nothing about the timing checks. The warnings make sense when you know the solution but they're not very helpful during debug. Problem solved! Andy
    • Post Points: 5
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Started by andymont at 23 May 2013 04:22 AM. Topic has 1 replies.