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 IO filler cell violations power routing 

Last post Wed, Jul 31 2013 8:33 AM by Kari. 1 replies.
Started by amythpai 14 May 2013 01:14 AM. Topic has 1 replies and 679 views
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  • Tue, May 14 2013 1:14 AM

    • amythpai
    • Not Ranked
    • Joined on Sun, Mar 17 2013
    • Lannion, Cotes-dArmor
    • Posts 14
    • Points 220
    IO filler cell violations power routing Reply

    Hello,

    I am trying to do the power routing of the IO pads in my design. I connected all the power and ground pins using global net connect command. 

     globalNetConnect vdd -type pgpin -pin {vdd} -inst * -module {} 

    globalNetConnect vdd -type pgpin -pin {vdds} -inst * -module {} 

    globalNetConnect vdd -type pgpin -pin {VDD} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {A0SRC} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {A1SRC} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {A2SRC} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {A3SRC} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {A4SRC} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {A5SRC} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {A6SRC} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {TRIGGER} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {BOOST} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {REFIO} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {gnd} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {gnds} -inst * -module {}

    globalNetConnect gnd -type pgpin -pin {GND} -inst * -module {}

    and then executed the Sroute command:

     sroute -connect { padPin } -layerChangeRange { M1 M7 } -blockPinTarget { nearestTarget } -padPinPortConnect { allPort oneGeom } -checkAlignedSecondaryPin 1 -allowJogging 1 -crossoverViaBottomLayer M1 -allowLayerChange 1 -targetViaTopLayer M7 -crossoverViaTopLayer M7 -targetViaBottomLayer M1 -viaConnectToShape { padring ring }

    But I got a lot of open violations on the IO filler cells that I have used in the design. please have a look at the image attached. Can anyone please tell me where I am going wrong

     

    Thank you 


    • Post Points: 20
  • Wed, Jul 31 2013 8:33 AM

    • Kari
    • Top 10 Contributor
    • Joined on Tue, Jul 15 2008
    • Cary, NC
    • Posts 693
    • Points 14,155
    Re: IO filler cell violations power routing Reply
    Are you sure those are really IO filler cells? IO Filler cells shouldn't have pins that need connecting.
    • Post Points: 5
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Started by amythpai at 14 May 2013 01:14 AM. Topic has 1 replies.