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 Need to place a pin on the symbol for an internal VerilogA signal 

Last post Wed, May 8 2013 8:59 AM by boast. 2 replies.
Started by boast 07 May 2013 04:01 PM. Topic has 2 replies and 1017 views
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  • Tue, May 7 2013 4:01 PM

    • boast
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    • Joined on Mon, Mar 25 2013
    • Posts 3
    • Points 45
    Need to place a pin on the symbol for an internal VerilogA signal Reply

    I have an internal signal in my VerilogA code that is passed to another module, and it is not on this module's port list. But when netlisting, it complains that it wants a pin on the symbol for that signal. 

     So my temporary solution is just to place it on the symbol and then as a no-connect on a schematic. But is it normal for internal signals to have pins on the symbol only because it will be passed to another module internally?

     

    Thanks. 

    • Post Points: 20
  • Wed, May 8 2013 6:09 AM

    Re: Need to place a pin on the symbol for an internal VerilogA signal Reply

    So how are you expecting to connect to this internal node? Normally connections would only be through the external connections of a module.

    It's not obvious to me what you mean - maybe you can illustrate it with an example?

    Kind Regards,

    Andrew.

    • Post Points: 20
  • Wed, May 8 2013 8:59 AM

    • boast
    • Not Ranked
    • Joined on Mon, Mar 25 2013
    • Posts 3
    • Points 45
    Re: Need to place a pin on the symbol for an internal VerilogA signal Reply

    The internal signal is assigned within the module, in my analog block. Having that pin on my symbol, it connects to nothing on my test bench. 

     `include block_2

    module block_1(a,b,c);

    ... 

    electrical d;

    block_2 name0 (a,d);

    analog

    V(d,b) <+ value; 

     endmodule 

    So signal d is set and assigned internally, and passed to another module. When I set block_1 on my schematic, I have nothing to connect to signal d, but cadence requires a pin on the symbol. 

     

    Edit: This is only if the internal signal is used in the analog block with V(signal,..) <+ 

    • Post Points: 5
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Started by boast at 07 May 2013 04:01 PM. Topic has 2 replies.