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 Unable to map design without a suitable latch. [MAP-3] [synthesize] 

Last post Thu, Jun 5 2014 9:25 AM by JustV. 2 replies.
Started by 20050710212 25 Apr 2013 08:46 AM. Topic has 2 replies and 6697 views
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  • Thu, Apr 25 2013 8:46 AM

    Unable to map design without a suitable latch. [MAP-3] [synthesize] Reply

    The same design can be synthesized by Synopsys (syn-2010.03-SP3). No error happens. When I use Cadence RTL compiler, one error happens. The error information is listed as below.

    Library:  CORE65GPLVT_nom_1.10V_25C.lib
                 CLOCK65GPLVT_nom_1.10V_25C.lib

    Error   : Unable to map design without a suitable latch. [MAP-3] [synthesize]
              : Instance 'U1/full_nx_reg' requires a simple latch.
              : Check the libraries for necessary latch cell. The cell could be marked unusable.
                Synthesis failed.

    Code: 

       WHEN "10" =>
                 IF (full_nx /= '1') THEN
                      wptr_nx <= wptr_reg;
                    empty_nx <= '0';    
                        wen_nx <= '1';
                         ren_nx <= '0';
                       IF (wen_nx = '1') THEN
                          wptr_nx <= wptr_suc;    
                       END IF;
                ELSE
                   wen_nx <= '0';
                   ren_nx <= '0';
                END IF;

                IF (wptr_suc = rptr_reg) THEN
                   full_nx <= '1';
                   wen_nx  <= '0';
                ELSE
                  full_nx <= '0';
                END IF;

    Could you please give me some suggestions? I 'd appreciate any help I can get.

    Thank you very much.

     

    Li

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    • Post Points: 20
  • Thu, Apr 25 2013 9:21 AM

    • Fotios Nt
    • Not Ranked
    • Joined on Fri, Nov 18 2011
    • Posts 5
    • Points 55
    Re: Unable to map design without a suitable latch. [MAP-3] [synthesize] Reply

     Hello Li,

     

    Your library doesnt seem to contain a latch. Please open it and ensure that you have latch cells, and they aren't marked unusable

     

    If you do not want to use latches, please take a look in the HDL Modeling in Encounter® RTL Compiler manual, where it is explained that , depending on the way you code verilog, synthesis can infer a latch rather than a flop in many situations.

     

    Regards,

    Fotis

     

    P.S: This topic should be moved to "Logic Design" board, because it is an RTL compiler issue, and not a C to Silicon one.

    • Post Points: 20
  • Thu, Jun 5 2014 9:25 AM

    • JustV
    • Not Ranked
    • Joined on Tue, Apr 15 2014
    • Posts 12
    • Points 30
    Re: Unable to map design without a suitable latch. [MAP-3] [synthesize] Reply

     Thanks for reply

    • Post Points: 5
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Started by 20050710212 at 25 Apr 2013 08:46 AM. Topic has 2 replies.