Before I answer the via variant question I would like to say that this is not normally necessary.
VSR can fix any jog errors if the DRC information is in the tech file.
You did not mention how you found the DRC errors. If you used an external checker, it is possible that the rules are not part of the Cadence tech lib. VSR uses the rules in the techlib.
An easy way to find out is to simply use the DRD batch checker.
Click verify->design and click the check box "process rules"
If the batch checker found the DRC errors then there must be a problem with the router sequencer setup.
Make sure that the option "Minimum Edge Length" is checked in the Refinement step (click the edit button in the sequencer.
If the checker found no errors then it is a problem with your PDK. The design rules are not sufficiently defined. Either contact your PDK provider or add the missing rules to your Constraint Group.
Back to your original question:
I just tested this out with the latest release ( IC6.1.5 ISR 16) and everything worked.
Perhaps you can try to get access to the latest release.
Also, your screenshot shows the rules for the Wire Assistant.
It looks like you created a Constraint Group from the Wire Assistant and then used this C.G as input to the router.
I would double-check by opening the Process-rule Editor (from the Constraint Manager) and making sure that the via variants are listed in the valid vias section
So I would try to find out the cause of the DRC errors because VSR should be able to handle this.
Hope this helps