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 Creating e Wrapper for system verilog code 

Last post Wed, Mar 27 2013 9:22 AM by Selvavinayak. 2 replies.
Started by Selvavinayak 27 Mar 2013 07:52 AM. Topic has 2 replies and 1383 views
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  • Wed, Mar 27 2013 7:52 AM

    • Selvavinayak
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    • Joined on Thu, May 10 2012
    • chennai, Tamil Nadu
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    Creating e Wrapper for system verilog code Reply

     Hi all,

        I am try to creating eRM Wrapper for  sv Environment. In that environment systemverilog tasks/function which is called from specman e methods. I have better knowledge in both Verification component. but i need how to interfere this both Verification component. if any body have an Idea about this. share your knowledge this will helpful for me to update

    example code:

    In Sv:

        function void m(bit [`ADDR_SIZE-1:0] addr,bit [`DATA_SIZE-1:0] data);

        $display("ADDR: %d",addr);
        $display("DATA: %d",data);
        $display("iam here");
        endfunction

    In eVC:

     .......here, how can i call above systemverilog function ?....

     

    Thanks & Bestregards,

    selvavinayakam.na

     

    • Post Points: 20
  • Wed, Mar 27 2013 8:40 AM

    • StephenH
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    • Bristol, Avon
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    Re: Creating e Wrapper for system verilog code Reply

    I'm not sure if I fully understood your intentions... There is a simple way to call individual SV functions from e, but you can also wrap complete UVCs so that the e env can instantiate and control a UVM-SV sequencer, driving sequences and transactions from e. There are examples for both, supplied in the tool installation as part of the SoC Verification Kit.

    For the UVC wrapping, the example files live under <incisive-install-dir>/kits/VerificationKit/soc_verification_lib/mixed_ex_lib/e_over_sv_class_lib/

    You can find a self-paced workshop with labs here: <incisive-install-dir>/doc/kit_topics/uvm_mixed/e_over_sv/workshop/Integrating_SV_UVC_in_e.pdf

     

    If however you just want to do a simple function call interface, take a look at "Using e Method Ports with SystemVerilog Functions and Tasks" in the cdnshelp tool. It's under the hierarchy:

    Specman Functional Verification ->  Specman Integrators Guide -> Integrating the e testbench with SystemVerilog

     

    Hope this helps. 

     

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
    • Post Points: 20
  • Wed, Mar 27 2013 9:22 AM

    • Selvavinayak
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    • Joined on Thu, May 10 2012
    • chennai, Tamil Nadu
    • Posts 11
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    Re: Creating e Wrapper for system verilog code Reply

    Hello Stephen, Thanks for your reply.

      I got key Idea about calling systemverilog function thro' e wrapper from a cdnshelp &[Using e Method Ports with SystemVerilog Functions and Tasks].Thanks alot for ur help

    Best Regards,

    selvavinayakam.na

     

     

    • Post Points: 5
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Started by Selvavinayak at 27 Mar 2013 07:52 AM. Topic has 2 replies.